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GD16523-100BA Datasheet

  • GD16523-100BA

  • PCM， Other/Special/Miscellaneous

  • 10頁(yè)

  • ETC

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2.5 Gbit/s
16:1 Multiplexer
GD16523
Preliminary
General Information
The GD16523 multiplexes sixteen data
inputs into a single data output, the bit
rates of the inputs are selectable (see
table below).
The data inputs are forward clocked by
the differential input (DCLKP / DCLKN).
The GD16523 tolerates up to 1.7 UI
PP
(155 MHz) jitter on the input data and for-
ward clock.
A double PLL system combined with an
elastic buffer ensures low output jitter.
Each PLL has a separate PCMOS lock-
detect output.
VBB
VBBS
Features
The VCXO reference clock input is differ-
ential and the frequency is selectable
78 MHz or 155 MHz.
Data inputs are differential LVPECL in-
puts. 2.5 GHz clock and data outputs are
differential CML with internal 50
鈩?/div>
termi-
nations.
The GD16523 requires only one supply
voltage of +3.3 V and consumes less
than 1 W.
The GD16523 is available in a 100 pin
TQFP package (14 脳 14 mm) with heat
slug on bottom surface.
LSEL
SLBOP
SLBON
l
l
l
l
l
l
l
l
2.5 Gbit/s 16:1 Multiplexer.
Forward clocked input data.
Differential reference clock input.
2.5 GHz clock output.
LVTTL lock detect outputs.
Single power supply: +3.3 V.
Power consumption: less than 1 W.
Available in a 100 pin TQFP package
(14 脳 14 mm) with exposed heat slug
on bottom surface.
DIP0
DIN0
DIP15
DIN15
DCLKP
DCLKN
16
16
Elastic
Buffer
IBR
W
IBR/2
IBR/2
R
IBR
16:1
MUX
OBR
DOUTP
DOUTN
/2
Narrow
band
LPF
CHAP1
CKOP
CKON
PFD1
/2
Clock
Generator
BRS0
BRS1
NLOCK1
NLDC1
CSEL
NLOCK2
VCXIP
VCXIN
PFD2
VCO
2.5 GHz
CHAP2
XSEL
SLTCK TCK
VCTL
NLDC2
VEE
VEEA
VCC
VCCA
VCXO
72 - 81 MHz
143 - 163 MHz
IBR = Input Bit Rate
OBR = Output Bit Rate
Wideband
LPF
BRS1
0
0
1
1
Data Sheet Rev. 11
BRS0
0
1
0
1
Input Bit Rate (IBR)
9.0 - 10.1 Mbit/s
36 - 40 Mbit/s
72 - 81 Mbit/s
143 - 163 Mbit/s
Output Bit Rate (OBR)
143 - 163 Mbit/s
575 - 650 Mbit/s
1150 - 1300 Mbit/s
2300 - 2600 Mbit/s

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