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GD16367B-52BA Datasheet

  • GD16367B-52BA

  • ATM Multiplexer

  • 14頁

  • ETC

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140 鈥?155 Mbit/s
CMI Encoder/
Decoder
GD16367B/GD16368B
Preliminary
General Description
The GD16367B and GD16368B is a
chip- set intended for use in SDH STM-1/
SONET OC-3 and PDH E4 systems,
where electrical CMI coded interface is
needed.
The chip set is designed to take care of
all processing above 78 MHz in an
STM-1/OC-3/E4 interface, accommodat-
ing both electrical (CMI) and optical
(NRZ) data format. Hence the same
board may be configured as STM-1o,
STM-1e, E4o, or E4e at system integra-
tion level.
encoder may be switched off when the
interface is optical.
Features
l
Integrates all high-speed signal
processing above 78 MHz.
ITU-T G.703 CMI encoding/decoding
for STM-1 and E4 electrical inter-
faces.
Meet G.751, G.823 and G.825 for
jitter tolerance and jitter generation.
Remote and local loops available.
CMI disable function for board level
configuration for optical interface.
Selectable 2, 4 or 8 bit parallel inter-
face for maximum flexibility.
Selectable 0擄, 90擄, 180擄, 270擄 phase
relation for parallel data I/O.
3.3 V LVPECL High speed I/O鈥檚.
CMOS Interface to system ASIC.
Power consumption typical:
鈥?400 mW for GD16367B
鈥?600 mW for GD16368B
3.3 V supply; 5 V for VCO.
Designed for low cost and volume
production.
High-speed BiCMOS technology.
Package 52 pin PQFP (10 x 10 mm).
The Decoder - GD16368B
The DeMUX/Decoder device provides
clock and data recovery extracting the
280/311 MHz clock of the incoming CMI
signal and a decoder that turns CMI to
NRZ. CMI code violations are detected
and signaled by the CODV output. The
CMI decoder may be switched off when
the interface is optical
Both devices provide selectable 2, 4 or
8 bit parallel interface to the processing
device for maximum flexibility.
The phase relation between parallel data
and clock is selectable in four phases
(0擄, 90擄, 180擄, 270擄) providing flexible
timing between the system and the
devices.
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The Encoder - GD16367B
The MUX/Encoder device generates the
CMI coded data signal and associated
clock at 280/311 MHz. The reference in-
put clock for the clock synthesis may be
selected from two individual inputs, 70/
78 MHz or 17/19 MHz allowing for pro-
grammable selection between reference
inputs for E4 or STM-1/OC-3. The CMI
SEL1
SIP
SIN
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SEL2
SEL3
PW1
PW2
SLB
LLB
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CMI / NRZ
DOU0
GD16368B
SLSIN
SLSIP
CKRF LLSOP LLSON LLCOP LLCON
DOU7
DOCK
CODV
2 / 4 / 8 bit NRZ
17 - 78 MHz
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STM-1 Processing ASIC
Line Interface Unit
CMI / NRZ
280 / 311 MHz
140 / 151 MHz
CKRU
LLSIP
LLSIN
LLCIP LLCIN
Applications
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SLSOP
SLSON
SOP
SON
CKO
CKN
DIN0
GD16367B
DIN7
DICK
2 / 4 / 8 bit NRZ
17 - 78 MHz
Tele Communication:
鈥?SDH STM-1
鈥?SONET OC-3
鈥?PDH E4
Data Sheet Rev. 14
STM-1
F4
VCO
LPF
PDH-REF
STM-REF
LLB
SLB
PW1
PW2
ICV
SEL1
SEL2
SEL3
SEL4

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