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GD16333-QFP100 Datasheet

  • GD16333-QFP100

  • ATM/SONET Demultiplexer

  • 122.08KB

  • 9頁

  • ETC

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622 MHz
4:32 Demultiplexer
GD16333
Preliminary
General Description
The GD16333 is 4:32 Demultiplexer, in-
tended for use with GD16544, an
STM-64 receiver and 1:16 Demultiplexer
or in DSP applications with fast ADC鈥檚.
The GD16333 consists of:
u
four 1:8 demultiplexers
u
a clock generator circuit
u
a synchronisation circuit.
The synchronisation circuit enables a
parallel coupling of several devices. This
is done with a master clock divider, which
distributes a synchronisation signal to the
parallel devices.
The GD16333 is provided in a 100 pin
power enhanced plastic package.
The chip is designed for operation be-
tween -5
EC
and +85
EC
(case tempera-
ture).
Features
l
l
Clock frequency to 622 MHz.
4:32 DeMUX obtained by four 1:8
DeMUX.
High-speed differential inputs,
CML/PECL level.
Data outputs are CMOS level.
100 pin QFP (14 x 20 mm) power
enhanced plastic package.
Power consumption: 1 W typical.
Synchronisation of parallel devices
for wider bus widths.
5 V single supply operation.
l
l
l
l
l
l
IN0
IN0N
O0, O4..O28
Applications
l
IN1
IN1N
O1, O5..O29
IN2
IN2N
Tele Communication:
鈥?STM-64
STM-16
鈥?OC-192
OC-48
DSP
鈥?High speed ADC interface
O2, O6..O30
l
IN3
IN3N
O3, O7..O31
TSTR
VCS
VEE
VDD
VDDC
SYNC
SYNCN
CLK
CLKN
Data Sheet Rev. 07
Div. 2 / 4 / 8
CKO
FCK
FCKN
Div. 8
SYNCO
SYNCON
FCKO
FCKON

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