HDTV
Deserialiser
GD14516A
Advance Information
The GD14516A High Definition TV
Deserialiser is designed for point-to-point
serial transmission systems for HDTV
signals according to SMPTE292.
The device provides a fully integrated
solution for:
u
Clock recovery and data re-timing at
1485 Mbit/s
u
Descrambler and NRZI decoder
u
Frame Detector for SAV/EAV
u
1:20 DeMUX.
The Clock and Data Recovery Circuit
consists of:
u
a Bang-Bang Phase Detector (PD)
with data re-timing
u
Phase-Frequency Comparator (PFC),
u
a Lock Detect Circuit (LCD)
with Lock Alarm Output,
u
a Tristatable Charge Pump
u
a wide tuning range VCO.
The VCO centre frequency is determined
by the REFCK multiplied by 20. The loop
filter time constant is determined by an
external RC filter.
When in lock, the digital
Lock Detect Cir-
cuit
uses the incoming data to control the
PLL. When not in lock, i.e. the VCO fre-
quency is more than 500 ppm away from
the REFCK frequency, the LDC switches
to the local clock (REFCK) until the VCO
frequency once more enters the
鹵500 ppm range. Then it switches back
to the PD, comparing the VCO clock to
the incoming data stream. The LDC con-
tinuously monitors the VCO frequency
against the REFCK input, clearing LOCK
if the VCO leaves the lock range.
A Frame Alignment circuit detects the
EAV/SAV framing pattern and aligns data
at the 20 bit output port. The frame align-
ment can be disabled to allow other
coding schemes.
The high-speed data input is differential
and compatible with PECL levels. It is
connected via loop-through transmission
lines to minimize stub related reflections.
For repeater applications a re-timed 75
S
cable driver output is provided, which
also can be used to drive an optical
module.
The GD14516A is packaged in a 68 pin
leaded Multi Layer Ceramic (MLC) pack-
age with cavity down for easy cooling.
Features
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Nominal data-rate 1485 Mbit/s NRZI.
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Two operating ranges:
鈥?/div>
鈥?/div>
1.2 -1.5 Gbit/s
300 - 375 Mbit/s
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Timing and Alignment Jitter in accor-
dance with SMPTE292.
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High-speed data input and output use
Loop-through bondings to reduce
reflections.
and Lock Acquisition on one IC.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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Complete Clock/20 (Data Recovery)
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Digitally controlled capture and lock.
Full capture range with true
Phase/Frequency detect between
VCO-CLK and REFCK.
Bang-Bang Phase Detector be-
tween VCO-CLK and DATA.
Lock in range 鹵500 ppm or
鹵2000 ppm referred to REFCK.
Lock Alarm Output.
l
End of Active Video (EAV) / Start of
VCC_DMX
VCC_CDR
CIP
VEE
V3V3 V3V3A
Active Video (SAV) detection and
alignment of the parallel 20 bit output
driver output with external termination
resistors.
l
Re-timed differential 75
鈩?/div>
cable
SIP
SIN
NEN
SEN
DEN
TCKEN
TCK
TCKN
VCTL
SOP
SON
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Supply operation: 5 V and 3.3 V.
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Power dissipation: 2500 mW typ.
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Power down modes for repeater
applications.
PAR
VCO
Div.
/4
DI
Bang
DO
Bang
U
Phase
D
Detector
NRZI
&
Scrambler
DOUT0
DeMUX
DOUT19
l
68 pin Multi Layer Ceramic (MLC)
Frame
Align.
FP
leaded package with transmission
lines.
FFIN
/20
Clock
Divide
Data Sheet Rev. 03
Lock
Detect
V
R
PFC
U
D
4:2
MUX
U
D
Charge
Pump
OUTCHP
SEL0
SEL1
REFCK
REFCKN
LOCK
Phase
Ctrl
Applications
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HDTV studio equipment.
CKOUT
CPH0/1
VCCA VCCD VCCO
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