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GC3011-PQ Datasheet

  • GC3011-PQ

  • DIGITAL RESAMPLER

  • 35頁

  • TI

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SLWS130
GC3011 DIGITAL RESAMPLER
1.0
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KEY FEATURES
80 million samples per second (MSPS) input rate
Fractional rate change down to 1/4
th
the input rate
Synchronization logic to allow multi-chip complex
data operation.
Multiple chips can be synchronized with fixed delay
offsets.
Two chips allow rate changes up or down.
12 bit data I/O
32 bit rate control accumulator
16 sample output FIFO
15 tap linear phase interpolator
4096 interpolation steps
80% input passband (0 to 0.4F
CK
)
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+/- 0.1 dB passband ripple
Less than +/- 0.02 degrees rms phase jitter
-73 dB image rejection
60 dB worst case NPR
Adaptive rate change to lock the resampling
ratio to the output clock rate
PLL/VCO to generate an output clock to
match the rate change
Microprocessor interface for control, output,
and diagnostics
Built in diagnostics
2W power at 50 MHz, 5 volts
520 mW at 30 MHz, 3.3 volts
100 pin QFP package
1.1
BLOCK DIAGRAM
A block diagram illustrating the major functions of the chip is shown in Figure 1
CV,FOZ,FIZ
DC[0:11]
12 bits
M/S FRST
DIN[0:11]
12 bits
OCK
SI
CK
TO ALL CIRCUITS
INTERPOLATION
CONTROL
INTERPOLATION
RATIO
AND MODES
MULTI-CHIP
SYNC
AND OFFSET
INTERPOLATION FILTER
15 TAPS
4096 STEPS
SYNC
CIRCUIT
OUTPUT
MODES
RESET
CLK IN
IN
EIN
EVAL
INTERPOLATION
RLL
ERROR
16 SAMPLE
FIFO
OUT
SI
CLK
OUT
ERROR
OUTPUT CLOCK
GENERATOR
(FIXED CLOCK MODE OR
PLL AND VCO)
CVOUT
SO
CVIN
A[0:3]
C[0:8]
CONTROL IFACE
4 bits
INTERPOLATION
RATIO
ERROR
DATA BYPASS
8 bits
INTERPOLATION
MODES
OUTPUT MUX AND FORMAT
R/W
CS
OUTPUT
MODES
12 bits
FE
HF DOUT[0:11] DVAL SO
CKOUT
CK2X
Figure 1. GC3011 Block Diagram
-1-
JULY 22, 1996
This document contains information which may be changed at any time without notice

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