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GBP32 Datasheet

  • GBP32

  • The GigaBridge Switched-PCI Controller|GBP Reset Design Note

  • 12頁(yè)

  • ETC

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GBP/Reset DN
August 1, 2002
Version 1.0
Reset Sequence Generation for the GBP
Design Note
1. INTRODUCTION
This design note defines the requirements for reset sequence generation for the GigaBridge GBP32
and GBP64 devices. Designers must ensure that the reset timing requirements are met in order for the
GBP devices to operate properly. In addition, all signals must meet full PCI compliant timing
requirements.
Section 2 shows the timing diagrams and specific timing requirements that must be met for proper GBP
device operation for the Primary Node. The designer can use any method desired to achieve these
timing requirements.
Section 3 shows the timing diagrams and specific timing requirements that must be met for proper GBP
device operation for the Secondary Node. The designer can use any method desired to achieve these
timing requirements.
Sections 4-7 show an implementation of reset logic that PLX designers have used in house. These
circuits and details are intended as an example and may not reflect the circuit needed to handle the
specific requirements of the customer system.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Section 4 lists the signals used in our sample circuit.
Section 5 describes the Primary Node operation and sample circuit.
Section 6 describes the Secondary Node operation and sample circuit.
Section 7 provides the Verilog code for the Primary Node sample circuit.
2. TIMING REQUIREMENTS 鈥?PRIMARY NODE
Table 1 shows the timing requirements for Primary Node operation. Figure 1 shows the timing diagram
for Primary Node operation when using Hardware Autoconfiguration. Figure 2 shows the timing
diagram for Primary Node operation when using Serial EEPROM configuration.
Table 1. Timing Requirements 鈥?Primary Node
Symbol
Tpp
Tda
Tpw
Trst
Tpr
Description
PwrOn# de-assertion to valid PCLK.
PCI clock can be present before PwrOn# de-assertion
RST# de-assertion to PwrOn# re-assertion
Second power-on-reset assertion width
Reset active time after power stable
PwrOn# de-assertion to RST# de-assertion
RST# final de-assertion to initial configuration to GBP device
Min
Max
500 ns
16 ms
1 ms
1 ms
15 碌s
32 ms
* Note: In the timing diagrams in Figures 1 and 2, the assertions and de-assertions of the signals specified
are not with respect to the PCLK signal.
錚?/div>
PLX Technology, Inc., 2002
PLX Technology, Inc, 870 Maude Avenue, Sunnyvale, CA 94085, Phone 408-774-9060, Fax 408-774-2169
Products and Company names are trademarks/registered trademarks of their respective holders.

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