S E M I C O N D U C T O R, I N C .
105 MHz. The outputs are available at either 1x and 2x or at 1x and
. When one of the Group A outputs (Q0鈥?/div>
Q2) is used as feedback to the PLL, all Group A outputs will be at f
REF
, and
all Group B (Q3鈥換6) and Group C (Q7鈥換10) outputs will be at 2x f
REF
.
When one of the Group B outputs is used as feedback to the PLL, all Group
A outputs will be at
1
/
2
x f
REF
and all Group B and Group C outputs will
be at f
REF
.
A very stable internal Phase-Locked Loop (PLL) provides low-jitter
operation. This completely self-contained PLL requires no external
capacitors or resistors. The PLL鈥檚 voltage-controlled oscillator (VCO) has a
frequency range from 280 MHz to 420 MHz. By feeding back one of the
output clocks to FBIN, the PLL continuously maintains frequency and
phase synchronization between the reference clock (REFCLK) and each of
the outputs. The Shift Select pins select the phase shift (鈥?t, 鈥搕, 0, or +t)
for Group C outputs (Q7鈥換10) with respect to REFCLK. The phase shift
increment (t) is equivalent to the VCO鈥檚 period (1/f
VCO
).
TriQuint鈥檚 patented output buffer design delivers a very low output-to-
output skew of 150 ps (max). The GA1088鈥檚 symmetrical TTL outputs are
capable of sourcing and sinking 30 mA.
鈥?Selectable Phase Shift:
鈥?t, 鈥搕, 0, and +t (t = 1/f
VCO
)
鈥?Low output-to-output skew:
150 ps (max) within a group
鈥?Near-zero propagation delay
鈥?50 ps + 500 ps (max) or
鈥?50 ps +700 ps (max)
鈥?TTL-compatible with 30 mA
output drive
鈥?28-pin J-lead surface-mount
package
For additional information and latest specifications, see our website:
www.triquint.com
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