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S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
FBIN
11
GA1085
S1
10
REFCLK
9
S0
8
F1
7
F0
6
GND
5
TEST
12
VDD
13
Phase
Detector
VCO
Phase
Select
4
VDD
3
2
Q10
Q9
11-Output
Configurable
Clock Buffer
Q0
14
GND
15
Q1
Q2
16
17
MUX
Divide Logic
梅4, 梅5, or 梅6
Output Buffers
Group A
Group
C
1
GND
28
27
Q8
Q7
Features
鈥?Wide frequency range:
24 MHz to 105 MHz
鈥?Output configurations:
Four outputs at f
REF
Four outputs at f
REF
/2
Two outputs at f
REF
/2
with adjustable phase
or
Five outputs at 2x f
REF
Three outputs at f
REF
Two outputs at f
REF
with adjustable phase
鈥?Selectable Phase Shift: 鈥?t, 鈥搕,
+t, and +2t (t = 1/f
VCO
)
鈥?Low output-to-output skew: 150
ps (max) within a group
鈥?Near-zero propagation delay:
鈥?50 ps +1000 ps (max)
鈥?TTL-compatible with 30 mA
output drive
鈥?28-pin J-lead surface-mount
package
VDD
18
Group
B
26
VDD
19
20
21
22
23
24
25
GND
Q3
Q4
VDD
Q5
Q6
GND
TriQuint鈥檚 GA1085 is a configurable clock buffer which generates 11 outputs
and operates over a wide range of frequencies鈥攆rom 24 MHz to 105 MHz.
The outputs are available at either 1x and 2x or at 1x and
1
/
2
x the reference
clock frequency, f
REF
. When one of the Group A outputs (Q4鈥換8) is used as
feedback to the PLL, all Group A outputs will be at f
REF
, and all Group B
(Q0鈥換3) and Group C (Q9, Q10) outputs will be at
1
/
2
x f
REF
. When one of
the Group B outputs is used as feedback to the PLL, all Group A outputs
will be at 2x
REF
and all Group B and Group C outputs will be at f
REF
. The
Shift Select pins select the phase shift (鈥?t, 鈥搕, +t or +2t) for Group C
outputs (Q9, Q10) with respect to REFCLK. The phase shift increment (t)
is equivalent to the VCO鈥檚 period (1/f
VCO
).
A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation.
This completely self-contained PLL requires no external capacitors or resistors.
The PLL鈥檚 Voltage-Controlled Oscillator (VCO) has a frequency range from
280 MHz to 420 MHz. By feeding back one of the output clocks to FBIN,
the PLL continuously maintains frequency and phase synchron-ization
between the reference clock (REFCLK) and each of the outputs.
TriQuint鈥檚 patented output buffer design delivers a very low output-to-output
skew of 150 ps (max). The GA1085鈥檚 symmetrical TTL outputs are capable
of sourcing and sinking 30 mA.
For additional information and latest specifications, see our website:
www.triquint.com
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SYSTEM TIMING
PRODUCTS
SYSTEMS TIMING
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3
4
5
6
7
8
9
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