Freescale Semiconductor, Inc.
鈩?/div>
G4 Architecture White Paper
Delivering Performance Enhancement in 60x Bus Mode
Susan Seale
You know the scenario: you鈥檝e just released the
greatest whiz-bang product to the networking
marketplace鈥攆antastic
features,
excellent
performance, and the right price. But right away,
you have to watch out for competitors approaching
from all sides. To maintain your leadership
position in the market, your mission鈥攕hould you
choose to accept it鈥攊s to upgrade your product鈥檚
performance (and of course lower its cost) with
minimal hardware and software redesign. Where
do you begin?
If your system is PowerPC-based, using the
MPC750 (G3) in particular, there are a variety of
options to consider. Some devices offer new
features. This makes the marketers happy. Most
new offerings deliver higher core frequency. Now
the software developers are happy. And many
PowerPC upgrades are drop-in replacements
because they have the same footprint as the device
you鈥檙e using today. Even the hardware team can
celebrate. Naturally, the right choice depends on
how in your current implementation your software
pushes the processor to its limits.
At this point in the analysis, most embedded
developers admit to one common bottleneck in the
processor subsystem: I/O bandwidth. No matter
how high you crank up the processor speed, how
big the on-chip caches are, or how fast the core can
execute an instruction, the limitation of your
system鈥檚 performance is dependent upon how
much data the processor can move in and out (with
signi鏗乧ant manipulation in between).
Freescale Semiconductor, Inc...
Even without discussing the bene鏗乼s of the
AltiVec鈩?processing unit available in G4
processors (let鈥檚 leave that exercise for an analysis
of SIMD-intensive applications.) or enhancements
offered by G4鈥檚 MPX bus mode option, there are
many reasons for choosing a G4-series processor
for your system. For now, let鈥檚 consider only those
bene鏗乼s which apply to PowerPC systems using
the conventional PowerPC instruction set and the
standard 60x bus mode.
May we introduce the MPC7400/7410 and the
MPC7440/7450 devices.
Bene鏗乼 1. Higher Sustainable System
Bus Bandwidth
鈥楶eak bandwidth,鈥?the maximum number of bytes
that can be transferred in a single cycle, is a purely
theoretical number. By contrast, 鈥榤aximum
bandwidth,鈥?the maximum number of bytes that
can be transferred over several transactions,
provides a value which takes into account the
memory system latency and the limitations
associated with the bus protocol, in this case the
60x bus. For example, the 60x bus requires one
dead cycle between address tenures and one dead
cycle between data tenures. In a real system, I/O
bandwidth is further limited by particular device
implementation constraints. (Refer to Bene鏗乼 2
below for more detail on one of the architectural
constraints of the MPC750鈥攖he inability to
pipeline cache loads.) 鈥楽ustainable bandwidth鈥?/div>
means the maximum number of bytes that can be
transferred over an extended number of cycles,
taking into account all of the constraints mentioned
above.
Performance Enhancement
This paper highlights ways that the PowerPC
MPC74xx (G4) series can improve the I/O
bandwidth of your G3 system with minimal
engineering effort and can help you overcome the
barrier to best-in-class system performance.
漏 Motorola, Inc., 2001. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
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