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FW804-09-DB Datasheet

  • FW804-09-DB

  • PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device

  • 24頁(yè)

  • AGERE

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Data Sheet, Rev. 3
June 2001
FW804 PHY
IEEE
* 1394A
Four-Cable Transceiver/Arbiter Device
Distinguishing Features
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I
Supports LPS/link-on as a part of PHY-link inter-
face.
Supports provisions of
IEEE
1394-1995
Standard
for a High Performance Serial Bus.
Fully interoperable with
FireWire
鈥?/div>
implementation
of
IEEE
1394-1995.
Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
Separate cable bias and driver termination voltage
supply for each port.
Compliant with
IEEE
P1394a Draft 2.0
Standard
for a High Performance Serial Bus
(Supple-
ment)
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
While unpowered and connected to the bus, will not
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port.
Does not require external filter capacitors for PLL.
Does not require a separate 5 V supply for 5 V link
controller interoperability.
Interoperable across 1394 cable with 1394 physical
layers (PHY) using 5 V supplies.
Interoperable with 1394 link-layer controllers using
5 V supplies.
Powerdown features to conserve energy in battery-
powered applications include:
鈥?Device powerdown pin.
鈥?Link interface disable using LPS.
鈥?Inactive ports power down.
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
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Other Features
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80-pin TQFP package.
Single 3.3 V supply operation.
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at
50 MHz.
Node power-class information signaling for system
power management.
Multiple separate package signals provided for
analog and digital supplies and grounds.
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Features
I
Provides four fully compliant cable ports at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
Fully supports open HCI requirements.
Supports arbitrated short bus reset to improve
utilization of the bus.
Supports ack-accelerated arbitration and fly-by
concatenation.
Supports connection debounce.
Supports multispeed packet concatenation.
Supports PHY pinging and remote PHY access
packets.
Fully supports suspend/resume.
Supports PHY-link interface initialization and reset.
Supports 1394a-2000 register set.
Description
The Agere Systems Inc. FW804 device provides the
analog physical layer functions needed to implement
a four-port node in a cable-based
IEEE
1394-1995
and
IEEE
1394a-2000 network.
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*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
鈥?/div>
FireWire
is a registered trademark of Apple Computer, Inc.
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