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FS6232-01 Datasheet

  • FS6232-01

  • TWO WAY MP MOTHERBOARD CLOCK GENERATOR IC

  • 14頁

  • ETC

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FS6232
-01
AMERICAN MICROSYSTEMS, INC.
Two-Way MP Motherboard Clock Generator IC
September 2000
1.0
鈥?/div>
Features
Figure 1: Block Diagram
XIN
XOUT
ISEL_0:1
IREF
梅1
PWR_DWN#
SS_EN#
SEL133/100#
SEL_A:B
SSCG
PLL
Control
梅2
梅3
梅4
delay
Generates all clocks required for single and two-way
multi-processor (MP) platforms, including:
M
Four differential current-mode Host clock pairs
M
Four 66.67MHz 3.3V CK66 clock outputs
M
Ten 33.3MHz 3.3V PCI clock outputs
M
Two 3.3V Memory Reference clock outputs
M
Two 48MHz 3.3V CK48 clock outputs
M
Two buffered copies of the crystal reference
Control of current-mode Host clocks via IREF current
programming pin and ISEL_0:1 current multiplier pins
Host clock frequency selection via the SEL_A,
SEL_B, and SEL133/100# pins
Active-low PWR_DWN# signal allows one complete
clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLLs, and outputs
Spread-spectrum modulation (-0.5% at 31.5kHz) of
SSCG PLL clocks, enabled via SS_EN# input
Supports test mode and tristate output control to fa-
cilitate board testing
Available in a 56-pin SSOP and TSSOP
Crystal
Oscillator
adjust
VDD_R
REF_0:1
VSS_R
VDD_H
HOST_P1:4
HOST_N1:4
VSS_H
VDD_66
鈥?/div>
鈥?/div>
鈥?/div>
CK66_0:3
VSS_66
VDD_P
梅2
PCI_0:9
VSS_P
VDD_M
梅4
MREF_P
MREF_N
VSS_M
VDD_48
鈥?/div>
鈥?/div>
鈥?/div>
PLL
CK48_0:1
VSS_48
FS6232
Figure 2: Pin Configuration
VSS_R 1
56 VDD_M
55 MREF_P
54 MREF_N
53 VSS_M
52 SS_EN#
51 HOST_P1
50 HOST_N1
49 VDD_H
48 HOST_P2
47 HOST_N2
46 VSS_H
45 HOST_P3
44 HOST_N3
43 VDD_H
42 HOST_P4
41 HOST_N4
40 VSS_H
39 IREF
38 VDD
37 VSS
36 VDD_66
35 CK66_0
34 CK66_1
33 VSS_66
32 VSS_66
31 CK66_2
30 CK66_3
29 VDD_66
REF_0 / ISEL_0 2
REF_1 / ISEL_1 3
Table 1: Clock Parameters
CLOCK
GROUP
HOST_P
HOST_N
MREF_P
MREF_N
CK66
PCI
CK48
REF
#
PINS
4
4
1
1
4
10
2
2
3.3V
VDD_H
SUPPLY
VOLTAGE
SUPPLY
GROUP
FREQ.
(MHz)
133.33
100.00
66.67
50.00
66.67
33.33
48.008
14.318
PHASE
0擄
180擄
0擄
180擄
0擄
0擄
0擄
0擄
SKEW
(MAX)
150ps
Pair to
Pair
-
250ps
300ps
-
-
VDD_R 4
XIN 5
XOUT 6
VSS_P 7
PCI_0 8
PCI_1 9
VDD_P 10
PCI_2 11
PCI_3 12
VSS_P 13
PCI_4 14
PCI_5 15
VDD_P 16
PCI_6 17
PCI_7 18
Pair 1
Pair 2
3.3V
3.3V
3.3V
3.3V
3.3V
VDD_M
VDD_66
VDD_P
VDD_48
VDD_R
Pair 3
FS6232-01
Pair 4
Table 2: Clock Offsets
RELATION
CK66 leads PCI
PHASE
0擄
MIN
1.5ns
TYP
MAX
3.5ns
VSS_P 19
PCI_8 20
PCI_9 21
VDD_P 22
SEL133/100# 23
VSS_48 24
CK48_0 / SEL_A 25
CK48_1 / SEL_B 26
VDD_48 27
PWR_DWN# 28
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
ISO9001
9.18.00
IntSKS

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