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FS6070-01 Datasheet

  • FS6070-01

  • Buffer/Driver

  • 7頁

  • ETC

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FS6070-01
1:4 HSTL to LVTTL Fanout Buffer IC
1.0
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Features
Table 1: Clock Enable Configuration
CONTROL
OE_0
0
0
0
1
1
1
1
OE_1
0
1
1
0
0
1
1
DIVSEL
X
0
1
0
1
0
1
CLOCK OUTPUTS
Q0_1:2
Tristate
Tristate
Tristate
HREF 梅 3
HREF 梅 4
HREF 梅 3
HREF 梅 4
Q1_3:4
Tristate
HREF 梅 3
HREF 梅 4
Tristate
Tristate
HREF 梅 3
HREF 梅 4
Distributes one differential HSTL reference clock to
two banks of two single-ended LVTTL outputs
DIVSEL pin selects output divide-by-three or divide-
by-four of input frequency
LVTTL output-enable control for each bank
Input-to-output propagation delay: 5ns at 66.7MHz
16-pin (0.150鈥? SOIC and (4.4mm) TSSOP available
Figure 1: Pin Configuration
DIVSEL
VDD
VDD
HREF_P
HREF_N
VSS
VSS
OE_0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VDD
Q0_1
Q0_2
Q1_3
Q1_4
VSS
OE_1
Table 2: Pin Descriptions
Key: DI = Digital Input; DI = Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down;
DIO = Digital Input/Output; DO = Digital Output; P = Power/Ground; # = Active-low pin
U
Figure 2: Block Diagram
OE_0
VDD
FS6070
PIN
4
5
14
13
12
11
1
8
TYPE
AI
AI
DO
DO
DO
DO
DI
DI
DI
P
P
NAME
HREF_P
HREF_N
Q0_1
Q0_2
Q1_3
Q1_4
DIVSEL
OE_0
OE_1
VDD
VSS
DESCRIPTION
HSTL input (true)
HSTL input (complement)
LVTTL clock output
LVTTL clock output
LVTTL clock output
LVTTL clock output
Divider selection control input
Bank 0 output enable control; also used
with DIVSEL, OE_1 to select dividers
Bank 1 output enable control; also used
with DIVSEL, OE_0 to select dividers
3.3V power supply
Ground
Differential
Input
Output
Bank 0
Output
Bank 1
Q0_1
Q0_2
HREF_P
HREF_N
Q1_3
Q1_4
OE_1
VSS
9
2, 3,
15,16
6,
7, 10
Figure 3: Divide-by-3, Divide-by-4 Timing
HREF_N
HREF_P
Q0_1:2, Q1_3:4
(divide by 4)
Q0_1:2, Q1_3:4
(divide by 3)
t
pHL
t
pLH
t
pHL
t
pLH
V
X
FS6070
This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
ISO9001
QS9000
2.27.02

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