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FS6053 Datasheet

  • FS6053

  • LOW-SKEW CLOCK FANOUT BUFFER ICs

  • 19頁

  • ETC

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April 1999
1.0
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Features
2.0
Description
Generates up to eighteen low-skew, non-inverting
clocks from one clock input
Supports up to four SDRAM DIMMs
2
Uses either I C
鈩?/div>
-bus or SMBus serial interface with
Read and Write capability for individual clock output
control
Output enable pin tristates all clock outputs to facili-
tate board testing
Clock outputs skew-matched to less than 250ps
Less than 5ns propagation delay
Output impedance: 17鈩?at 0.5V
DD
Serial interface I/O meet I C specifications; all other
I/O are LVTTL/LVCMOS-compatible
Five differerent pin configurations available:
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FS6050: 18 clock outputs in a 48-pin SSOP
FS6051: 10 clock outputs in a 28-pin SOIC, SSOP
FS6053: 13 clock outputs in a 28-pin SOIC
FS6054: 14 clock outputs in a 28-pin SOIC
2
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鈥?/div>
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The FS6050 family of CMOS clock fanout buffer ICs are
designed for high-speed motherboard applications, such
廬
as Intel Pentium II PC100-based systems with 100MHz
SDRAM.
Up to eighteen buffered, non-inverting clock outputs are
fanned-out from one clock input. Individual clocks are
skew matched to less than 250ps at 100MHz. Multiple
power and ground supplies reduce the effects of supply
noise on device performance.
2
Under I C-bus control, individual clock outputs may be
turned on or off. An active-low output enable is available
to force all the clock outputs to a tristate level for system
testing.
Figure 2: Pin Configuration (FS6050)
SDRAM_15
SDRAM_14
SDRAM_13
SDRAM_12
SDRAM_11
SDRAM_10
SDRAM_17
SDRAM_9
SDRAM_8
(reserved)
(reserved)
VDD
VSS
VSS
27
VSS_I
2
C
26
23
VDD
VDD
VDD
VDD
VSS
VSS
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Figure 1: Block Diagram (FS6050)
10
FS6050
11
12
13
14
15
16
17
18
19
20
21
22
VDD
(reserved)
(reserved)
SDRAM_3
SDRAM_4
SDRAM_5
SDRAM_6
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_7
SDRAM_16
VDD
VDD
VDD
VDD
CLK_IN
VDD
VDD_I
2
C
VSS
VSS
VSS
VSS
VSS
SDRAM_(0:1)
VDD_I
2
C
VSS
VDD
SDA
Serial
Interface
SCL
VSS_I
2
C
18
SDRAM_(2:3)
VSS
VDD
48-pin SSOP
SDRAM_(4:5)
VSS
VDD
SDRAM_(6:7)
CLK_IN
VSS
VDD
Figure 3: Pin Configuration (FS6051)
SDRAM_15
SDRAM_14
SDRAM_13
SDRAM_12
SDRAM_17
VDD
VDD
VDD
VSS
VSS
VSS_I
2
C
VSS
OE
SCL
SDRAM_(8:9)
VSS
VDD
28
27
26
25
24
23
22
21
20
19
18
17
16
VSS
VDD
SDRAM_(12:13)
VSS
VDD
FS6051
10
11
12
13
14
1
2
3
4
5
6
7
8
9
SDRAM_(14:15)
VSS
VDD
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_16
VDD_I
2
C
VDD
VDD
CLK_IN
VDD
SDRAM_16
OE
VSS
VDD
SDRAM_17
VSS
28-pin SOIC, SSOP
FS6050
Additional pin configurations are noted on Page 2.
,62
Intel and Pentium are registered trademarks of Intel Corporation. I
2
C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-
tions as may be required to permit improvements in the design of its products.
4.5.99
SDA
VSS
VSS
VSS
15
SDRAM_(10:11)
SDA
24
1
2
3
4
5
6
7
8
9
25
SCL
OE

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