音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

FS6011-02 Datasheet

  • FS6011-02

  • DIGITAL AUDIO/VIDEO CLOCK GENERATOR IC

  • 234.49KB

  • 15頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

 
   X  T
'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,&
)6
July 1998
1.0
鈥?/div>
Features
2.0
Description
Triple phase-locked loop (PLL) device provides exact
ratiometric derivation of Audio, Processor, and Utility
Clocks
On-chip tunable voltage-controlled crystal oscillator
(VCXO) allows precise system frequency tuning
Serial interface for Audio and Utility Clock frequency
selection
Board-programmable Processor Clock frequency
selection
Supports 32, 44.1, and 48kHz 256x oversampled
DACs as well as 384x at 44.1kHz and 512x at 48kHz
Tunable Audio Clock frequencies for undetectable
resynchronization of audio and video streams
Small circuit board footprint (16-pin 0.150鈥?SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
The FS6011-02 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6011-02 is circuitry that implements
a voltage-controlled crystal oscillator when an external
resonator (nominally 27MHz) is attached. The VCXO al-
lows device frequencies to be precisely adjusted for use
in systems that have frequency matching requirements,
such as digital satellite receivers.
Three high-resolution phase-locked loops independently
generate three other selectable frequencies derived from
the VCXO frequency. These clock frequencies are re-
lated to the VCXO frequency and to each other by exact
ratios. The locking of all the output frequencies together
can eliminate unpredictable artifacts in video systems
and unpredictable electromagnetic interference (EMI)
performance due to frequency harmonic stacking.
Figure 1: Block Diagram
PSEL0
PSEL1
Processor
Clock PLL
PCLK
Figure 2: Pin Configuration
SCLK
SDATA
1
2
3
16
15
14
CLK27
ACLK
VDD
UCLK
PCLK
VSS
PSEL0
PSEL1
XTUNE
XIN
VCXO
XOUT
Audio
Clock PLL
ACLK
SLOAD
VSS
XIN
FS6011
4
5
6
7
8
13
12
11
10
9
Utility
Clock PLL
UCLK
XOUT
XTUNE
SLOAD
SCLK
SDATA
CLK_27
Serial
Interface
VDD
FS6011
16-pin (0.150鈥? SOIC
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
,62
7.20.98

FS6011-02相關(guān)型號(hào)PDF文件下載

掃碼下載APP,
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù):
賣家服務(wù):
技術(shù)客服:

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào),
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人:

聯(lián)系方式:

按住滑塊,拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見,您的參與是維庫(kù)提升服務(wù)的動(dòng)力!意見一經(jīng)采納,將有感恩紅包奉上哦!