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FQU3N50C Datasheet

  • FQU3N50C

  • 500V N-Channel MOSFET

  • 9頁(yè)

  • FAIRCHILD

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FQD3N50C/FQU3N50C 500V N-Channel MOSFET
QFET
FQD3N50C/FQU3N50C
500V N-Channel MOSFET
Features
鈥?2.5 A, 500 V, R
DS(on)
= 2.5
鈩?/div>
@ V
GS
= 10 V
鈥?Low gate charge ( typical 10 nC )
鈥?Low Crss ( typical 8.5 pF)
鈥?Fast switching
鈥?100 % avalanche tested
鈥?Improved dv/dt capability
廬
Description
These N-Channel enhancement mode power field effect transis-
tors are produced using Fairchild鈥檚 proprietary, planar stripe,
DMOS technology.
This advanced technology has been especially tailored to mini-
mize on-state resistance, provide superior switching perfor-
mance, and withstand high energy pulse in the avalanche and
commutation mode. These devices are well suited for high effi-
ciency switched mode power supplies, active power factor cor-
rection, electronic lamp ballasts based on half bridge topology.
D
D
鈼?/div>
鈼€
G
S
D-PAK
FQD Series
I-PAK
G D S
FQU Series
G
鈻?/div>
鈼?/div>
鈼?/div>
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
Drain Current
Drain Current
Parameter
Drain-Source Voltage
- Continuous (T
C
= 25擄C)
- Continuous (T
C
= 100擄C)
- Pulsed
(Note 1)
FQD3N50C/FQU3N50C
500
2.5
1.5
10
鹵
30
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/擄C
擄C
擄C
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
C
= 25擄C)
- Derate above 25擄C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
200
2.5
3.5
4.5
35
0.28
-55 to +150
300
Thermal Characteristics
Symbol
R
胃JC
R
胃JA
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient*
Thermal Resistance, Junction-to-Ambient
Typ
--
--
--
Max
3.5
50
110
Units
擄C/W
擄C/W
擄C/W
* When mounted on the minimum pad size recommended (PCB Mount)
漏2005 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FQD3N50C/FQU3N50C Rev. A

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