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FQS4900 Datasheet

  • FQS4900

  • Dual N & P-Channel, Logic Level MOSFET

  • 9頁(yè)

  • FAIRCHILD

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FQS4900
August 2000
QFET
FQS4900
Dual N & P-Channel, Logic Level MOSFET
General Description
These dual N and P-channel enhancement mode power
field effect transistors are produced using Fairchild鈥檚
proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. This device is well
suited for high interface in telephone sets.
TM
Features
鈥?N-Channel 1.3A, 60V, R
DS(on)
= 0.55
鈩?/div>
@ V
GS
= 10 V
R
DS(on)
= 0.65
鈩?/div>
@ V
GS
= 5 V
P-Channel -0.3A, -300V, R
DS(on)
= 15.5
鈩?/div>
@ V
GS
= -10 V
R
DS(on)
= 16
鈩?/div>
@ V
GS
=- 5 V
鈥?Low gate charge ( typical N-Channel 1.6 nC)
( typical P-Channel 3.6 nC)
鈥?Fast switching
鈥?Improved dv/dt capability
5
!
!
4
"!
!
!
D2
D2
D1
D1
6
3
G2
S2
G1
S1
7
!
!
2
#
$
!
!
8
1
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
dv/dt
P
D
T
J
, T
STG
T
A
= 25擄C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (T
A
= 25擄C)
Drain Current
- Continuous (T
A
= 70擄C)
Drain Curent
- Pulsed
(Note 1)
N-Channel
60
1.3
0.82
5.2
鹵
20
(Note 2)
P-Channel
-300
-0.3
-0.19
-1.2
4.5
2.0
1.3
Units
V
A
A
A
V
V/ns
W
W
擄C
Gate-Source Voltage
Peak Diode Recovery dv/dt
Power Dissipation (T
A
= 25擄C)
(T
A
= 70擄C)
Operating and Storage Temperature Range
7.0
-55 to +150
Thermal Characteristics
Symbol
R
胃JA
Parameter
Thermal Resistance, Junction-to-Ambient
Typ
--
Max
62.5
Units
擄C/W
漏2000 Fairchild Semiconductor International
Rev. A, August 2000

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