鈩?/div>
@ V
GS
= 10 V
鈥?Low gate charge ( typical 10 nC )
鈥?Low Crss ( typical 8.5 pF)
鈥?Fast switching
鈥?100 % avalanche tested
鈥?Improved dv/dt capability
廬
Description
These N-Channel enhancement mode power field effect transis-
tors are produced using Fairchild鈥檚 proprietary, planar stripe,
DMOS technology.
This advanced technology has been especially tailored to mini-
mize on-state resistance, provide superior switching perfor-
mance, and withstand high energy pulse in the avalanche and
commutation mode. These devices are well suited for high effi-
ciency switched mode power supplies, active power factor cor-
rection, electronic lamp ballasts based on half bridge topology.
D
鈼?/div>
鈼€
G
G DS
鈻?/div>
鈼?/div>
鈼?/div>
TO-220
FQP Series
GD S
TO-220F
FQPF Series
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
Drain Current
Parameter
Drain-Source Voltage
- Continuous (T
C
= 25擄C)
- Continuous (T
C
= 100擄C)
FQP3N50C
500
3
1.8
(Note 1)
FQPF3N50C
3*
1.8 *
12 *
鹵
30
200
3
6.2
4.5
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/擄C
擄C
擄C
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
Drain Current
- Pulsed
12
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
C
= 25擄C)
- Derate above 25擄C
(Note 2)
(Note 1)
(Note 1)
(Note 3)
62
0.5
-55 to +150
300
25
0.2
T
J
, T
STG
T
L
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
* Drain current limited by maximum junction temperature
Thermal Characteristics
Symbol
R
胃JC
R
胃JS
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink Typ.
Thermal Resistance, Junction-to-Ambient
FQP3N50C
2.0
0.5
62.5
FQPF3N50C
4.9
--
62.5
Units
擄C/W
擄C/W
擄C/W
漏2005 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FQP3N50C/FQPF3N50C Rev. A
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