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FQD2N100 Datasheet

  • FQD2N100

  • 1000V N-Channel MOSFET

  • 623.42KB

  • 9頁

  • FAIRCHILD

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FQD2N100/FQU2N100
February 2002
FQD2N100/FQU2N100
1000V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild鈥檚 proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for electronic lamp starter and ballast.
Features
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1.6A, 1000V, R
DS(on)
= 9鈩?@V
GS
= 10 V
Low gate charge ( typical 12 nC)
Low Crss ( typical 5 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
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G
S
D-PAK
FQD Series
I-PAK
G D S
FQU Series
G
!
!
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
C
= 25擄C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (T
C
= 25擄C)
Drain Current
- Continuous (T
C
= 100擄C)
Drain Current
- Pulsed
(Note 1)
FQD2N100/FQU2N100
1000
1.6
1.0
6.4
鹵
30
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/擄C
擄C
擄C
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
A
= 25擄C) *
Power Dissipation (T
C
= 25擄C)
160
1.6
5.0
5.5
2.5
50
0.4
-55 to +150
300
T
J
, T
STG
T
L
- Derate above 25擄C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
R
胃JC
R
胃JA
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
Typ
--
--
--
Max
2.5
50
110
Units
擄C/W
擄C/W
擄C/W
* When mounted on the minimum pad size recommended (PCB Mount)
漏2002 Fairchild Semiconductor Corporation
Rev. A, February 2002

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