鈥?/div>
7A, 650V, R
DS(on)
= 1.4鈩?@V
GS
= 10 V
Low gate charge ( typical 28 nC)
Low Crss ( typical 12 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
September 2006
廬
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild鈥檚 proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies, active power factor
correction, electronic lamp ballast based on half bridge
topology.
D
D
G
G
S
D
2
-PAK
FQB Series
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (T
C
= 25擄C)
- Continuous (T
C
= 100擄C)
- Pulsed
(Note 1)
Parameter
FQB7N65C
650
7
4.45
28
鹵
30
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/擄C
擄C
擄C
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
C
= 25擄C)
- Derate above 25擄C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
212
7
17.3
4.5
173
1.38
-55 to +150
300
Thermal Characteristics
Symbol
R
胃JC
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
FQB7N65C
0.75
62.5
Units
擄C/W
擄C/W
漏2006 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FQB7N65C Rev. A