FQB3N60C 600V N-Channel MOSFET
May 2006
QFET
FQB3N60C
600V N-Channel MOSFET
Features
鈥?3A, 600V, R
DS(on)
= 3.4惟 @ V
GS
= 10 V
鈥?Low gate charge ( typical 10.5 nC)
鈥?Low C
rss
( typical 5 pF)
鈥?Fast switching
鈥?100% avalanche tested
鈥?Improved dv/dt capability
TM
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild鈥檚 proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficiency switched mode power supplies, active power factor
correction, electronic lamp ballasts based on half bridge
topology.
D
D
G
S
D
2
-PAK
FQB Series
G
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J,
T
STG
T
L
Drain-Source Voltage
Drain Current
Drain Current
Gate-Source voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
(T
C
= 25擄C)
- Derate above 25擄C
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Parameter
- Continuous (T
C
= 25擄C)
- Continuous (T
C
= 100擄C)
- Pulsed
(Note 1)
FQB3N60C
600
3
1.8
12
鹵30
150
3
7.5
4.5
75
0.62
-55 to +150
300
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/擄C
擄C
擄C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purpose,
1/8鈥?from Case for 5 Seconds
Thermal Characteristics
Symbol
R
胃JC
R
胃JA
*
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient*
Thermal Resistance, Junction-to-Ambient
Typ.
--
--
--
Max.
1.67
40
62.5
Unit
擄C/W
擄C/W
擄C/W
* When mounted on the minimum pad size recommended (PCB Mount)
漏2006 Fairchild Semiconductor Corporation
FQB3N60C REV. A1
1
www.fairchildsemi.com