FPD95120 320-Channel LTPS/CGS Driver with MPL1 Interface
PRELIMINARY
June 2007
FPD95120
320-Channel LTPS/CGS Driver with MPL1 Interface
General Description
The FPD95120 is a 320鈥揷hannel LTPS/CGS driver with Par-
tial Display Memory, a 24鈥揵it RGB video interface and en-
hanced display quality. It provides 320 output source drivers
with a 1:3 glass multiplex ratio. It includes a 230,400鈥揵it
memory for partial display modes, a timing controller with
glass interface level-shifters, AC and DC V
COM
drive schemes
and glass power supply circuits. The output format can be
configured to drive arbitrary display resolutions up to 320RGB
columns. Advanced processing features enable up-scaling of
incoming video to accommodate legacy graphics. There is
also an upscale function for the Partial Display window to en-
able larger window sizes.
The on-chip Partial Display Memory is configurable in window
size, location and color depth. This memory can support par-
tial display windows such as 240x320 in 3鈥揵it mode and
320x720 in 1鈥揵it color mode. The partial display memory can
be used to self-refresh a region of the display in a reduced
power state or as an overlay for OSD and alpha-blending fea-
tures. The FPD95120 also includes independent RGB gam-
ma curve adjustments as well as user-definable color palettes
for 1鈥揵it and 3鈥揵it Partial Display modes.
A low-speed serial interface (LoSSI) is provided to control
display operating modes and provide access to the Partial
Display Memory. This interface can support both 8鈥揵it and 9鈥?/div>
bit protocols. A standard command set is supported to set
display modes and operating parameters. Customized regis-
ter profiles associated with each command are loaded from
an on-chip EEPROM. Registers can also be directly accessed
by using the Register Access Mode.
Features
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Power Savings
Self-refreshed Partial Display Mode
Provides timing signal for on-glass charge-sharing circuit
Standard Command Set
Registers initialized from on-chip EEPROM
Command-triggered profiles can change register settings
for modes/gamma settings
Eliminates frequent host SW changes to update register
settings
8 user-defined display configurations
Programmable Settings
Display resolution and glass signal timing
Video interface timing auto-learning circuit
VID_XFR output reduces tearing in partial mode
Gamma curves and V
COM
adjustment
Advanced Display Features
(evaluation only)
Configurable Partial Mode Window size, location and color
depth
Self-refreshed partial display mode supports 1鈥揵it and 3鈥?/div>
bit depths
OSD function with Partial RAM data in video mode
Alpha blending, including transparent mode
Video 2x upscale with programmable border
Partial Window 2x upscale with border color
Interfaces
Serial Interface (LoSSI) for commands, register access
and partial memory access
24鈥揵it RGB Video interface
MPL1 high-speed serial interface
System Diagrams
30025204
漏 2007 National Semiconductor Corporation
300252
www.national.com
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