鈥?/div>
DESCRIPTION AND APPLICATIONS
The FPD1050 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT),
featuring a 0.25
碌m
by 1050
碌m
Schottky barrier gate, defined by high-resolution stepper-based
photolithography. The recessed and offset Gate structure minimizes parasitics to optimize
performance. The epitaxial structure and processing have been optimized for reliable high-power
applications. The FPD750 also features Si
3
N
4
passivation and is also available in a low cost plastic
SOT89 plastic package.
Typical applications include commercial and other narrowband and broadband high-performance
amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output
amplifiers, and medium-haul digital radio transmitters.
鈥?/div>
ELECTRICAL SPECIFICATIONS AT 22擄C
Parameter
Power at 1dB Gain Compression
Maximum Stable Gain (S
21
/S
12
)
Power Gain at P
1dB
Power-Added Efficiency
Output Third-Order Intercept Point
(from 15 to 5 dB below P
1dB
)
Saturated Drain-Source Current
Maximum Drain-Source Current
Transconductance
Gate-Source Leakage Current
Pinch-Off Voltage
Gate-Source Breakdown Voltage
Gate-Drain Breakdown Voltage
Thermal Resistivity (see Notes)
Phone:
+1 408 850-5790
Fax:
+1 408 850-5766
Symbol
P
1dB
MSG
G
1dB
PAE
IP3
Test Conditions
V
DS
= 8 V; I
DS
= 50% I
DSS
V
DS
= 8 V; I
DS
= 50% I
DSS
V
DS
= 8 V; I
DS
= 50% I
DSS
V
DS
= 8 V; I
DS
= 50% I
DSS
;
P
OUT
= P
1dB
V
DS
= 10V; I
DS
= 50% I
DSS
Matched for optimal power
Tuned for best IP3
Min
27.5
10.0
Typ
28.5
14.0
11.0
45
Max
Units
dBm
dB
dB
%
RF SPECIFICATIONS MEASURED AT
f
= 12 GHz USING CW SIGNAL
39
41
250
315
520
280
15
1.0
16
16
18
18
45
375
dBm
I
DSS
I
MAX
G
M
I
GSO
|V
P
|
|V
BDGS
|
|V
BDGD
|
胃
JC
V
DS
= 1.3 V; V
GS
= 0 V
V
DS
= 1.3 V; V
GS
鈮?/div>
+1 V
V
DS
= 1.3 V; V
GS
= 0 V
V
GS
= -5 V
V
DS
= 1.3 V; I
DS
= 1 mA
I
GS
= 1 mA
I
GD
= 1 mA
V
DS
> 6V
http://
www.filcs.com
mA
mA
mS
碌A(chǔ)
V
V
V
擄C/W
Revised:
8/05/04
Email:
sales@filcsi.com
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