HIP6502B
TM
Data Sheet
May 2000
File Number
4871
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6502B complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
generates the 3.3V
DUAL
/3.3V
SB
voltage plane from the ATX
supply鈥檚 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply at choice either or both of the computer system鈥檚
2.5V or 3.3V memory power through external pass
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
powers up the 5V
DUAL
plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502B鈥檚 operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Enabling sleep state support on the
5V
DUAL
output is offered through the EN5VDL pin. In active
state, the 3.3V
DUAL
and 3.3V
MEM
linear regulators use
external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors -
external to the controller on the 3.3V
DUAL
, internal on the
3.3V
MEM
. Active state regulation on the 2.5V
MEM
output is
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5V
DUAL
output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current 鏗俹w is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5V
DUAL
output is dictated not only by the status of the
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3V
DUAL
/3.3V
SB
output is active for as long as the ATX
5VSB voltage is applied to the chip. The 2.5V
CLK
output is
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.
Features
鈥?Provides 5 ACPI-Controlled Voltages
- 5V
DUAL
USB/Keyboard/Mouse (Active/Sleep)
- 3.3V
DUAL
/3.3V
SB
PCI/Auxiliary/LAN (Active/Sleep)
- 2.5V
MEM
RDRAM (Active/Sleep)
- 3.3V
MEM
SDRAM (Active/Sleep)
- 2.5V
CLK
Clock/Processor Terminations (Active Only)
鈥?Excellent Output Voltage Regulation
- 3.3V
DUAL
/3.3V
SB
Output:
鹵2.0%
Over Temperature;
Sleep State Only
- 2.5V
MEM
and 3.3V
MEM
Output:
鹵2.0%
Over
Temperature; Both Operational States (3.3V
MEM
in
Sleep Only)
- 2.5V
CLK
Output:
鹵2.0%
Over Temperature
鈥?Small Size
- Very Low External Component Count
鈥?Dual Memory Voltage Support Via MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
- Both 2.5V and 3.3V for Flexible Systems
鈥?Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
鈥?Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6502B
(SOIC)
TOP VIEW
20 MSEL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
VSEN2
1
5VSB 2
VSEN1 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL
S3
8
9
Ordering Information
PART NUMBER
HIP6502BCB
HIP6502BEVAL1
TEMP.
RANGE (
o
C)
0 to 70
PACKAGE
20 Ld SOIC
PKG.
NO.
M20.3
S5 10
Evaluation Board
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Copyright
漏
Intersil Corporation 2000
INTERSIL
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