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FMS72509MTC Datasheet

  • FMS72509MTC

  • Ten Distributed-Output Clock Driver

  • 48.80KB

  • 7頁

  • ETC

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www.fairchildsemi.com
FMS72509
Phase Locked Loop Clock Driver
Features
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PC-133 Spread Spectrum Compliant
Frequency Range of 25 to 140 MHz
V
DD
Range of 3.0 to 3.6 Volts
Up to 11 outputs
Less than 100 pS of Output to Output Skew
Less than 90 pS of Cycle to Cycle Jitter
Output Enable pin
Integrated Damping Resistor
Commercial Temperature Range
Available in 24 pin TSSOP
Description
FMS72509 is a zero delay clock buffer designed for high fan
out applications. It contains 10 outputs. It provides precise
phase and frequency alignment between incoming clock and
the output clocks. This makes it ideal for high speed applica-
tion in the range of 25 to 140 MHz. The Phase Locked Loop
is capable of tracking incoming clock modulation of up to
鹵1% of the clock period. With the exception of FBOUT, the
output Enable (OE) pin, when pulled low, will force the out-
puts to logic low.
Block Diagram
OE1
FB O U T
Q0
Q1
Q2
Q3
FBIN
PLL
CLKIN
Control
Logic
Q4
Q5
Q6
Q7
Q8
Q9
OE2
REV. 1.0 8/11/00

FMS72509MTC 產(chǎn)品屬性

  • Fairchild Semiconductor

  • PLL Clock Driver

  • 1

  • 140 MHz

  • 25 MHz

  • 3.6 V

  • 3 V

  • + 70 C

  • 0 C

  • TSSOP-24

  • SMD/SMT

  • 3.3 V

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