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FIN1218MTD Datasheet

  • FIN1218MTD

  • LVDS 21-Bit Serializers/De-Serializers

  • 17頁(yè)

  • FAIRCHILD

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FIN1217 鈥?FIN1218 鈥?FIN1215 鈥?FIN1216 LVDS 21-Bit Serializers/De-Serializers
October 2003
Revised October 2004
FIN1217 鈥?FIN1218 鈥?/div>
FIN1215 鈥?FIN1216
LVDS 21-Bit Serializers/De-Serializers
General Description
The FIN1217 and FIN1215 transform 21-bit wide parallel
LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 21 bits of input LVTTL data are sampled and trans-
mitted.
The FIN1218 and FIN1216 receive and convert the 3 serial
LVDS data streams back into 21 bits of LVTTL data. Refer
to Table 1 for a matrix summary of the Serializers and De-
serializers available. For the FIN1217, at a transmit clock
frequency of 85 MHz, 21 bits of LVTTL data are transmitted
at a rate of 595 Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and
cable size problems associated with wide and high-speed
TTL interfaces.
Features
s
Low power consumption
s
20 MHz to 85 MHz shift clock support
s
50% duty cycle on the clock output of receiver
s
鹵
1V common-mode range around 1.2V
s
Narrow bus reduces cable size and cost
s
High throughput (up to 1.785 Gbps throughput)
s
Up to 595 Mbps per channel
s
Internal PLL with no external component
s
Compatible with TIA/EIA-644 specification
s
Devices are offered in 48-lead TSSOP packages
Ordering Code:
Order Number
FIN1215MTD
FIN1216MTD
FIN1217MTD
FIN1218MTD
Package Number
MTD48
MTD48
MTD48
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 2004 Fairchild Semiconductor Corporation
DS500876
www.fairchildsemi.com

FIN1218MTD 產(chǎn)品屬性

  • 38

  • 集成電路 (IC)

  • 接口 - 串行器，解串行器

  • -

  • 串行器/解串器

  • 1.785Gbps

  • LVDS

  • LVTTL

  • 3

  • 21

  • 3 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-TFSOP（0.240"，6.10mm 寬）

  • 48-TSSOP

  • 管件

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