FDD3N40 / FDU3N40 400V N-Channel MOSFET
February 2007
FDD3N40 / FDU3N40
400V N-Channel MOSFET
Features
鈥?2A, 400V, R
DS(on)
= 3.4鈩?@V
GS
= 10 V
鈥?Low gate charge ( typical 4.5 nC)
鈥?Low C
rss
( typical 3.7 pF)
鈥?Fast switching
鈥?100% avalanche tested
鈥?Improved dv/dt capability
UniFET
Description
TM
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild鈥檚 proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies and active power factor
correction.
D
D
G
S
D-PAK
FDD Series
I-PAK
G D S
FDU Series
G
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J,
T
STG
T
L
Drain-Source Voltage
Drain Current
Drain Current
Gate-Source voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
(T
C
= 25擄C)
- Derate above 25擄C
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Parameter
- Continuous (T
C
= 25擄C)
- Continuous (T
C
= 100擄C)
- Pulsed
(Note 1)
FDD3N40 / FDU3N40
400
2.0
1.25
8.0
鹵30
46
2
3
4.5
30
0.24
-55 to +150
300
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/擄C
擄C
擄C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purpose,
1/8鈥?from Case for 5 Seconds
* Drain current limited by maximum junction temperature
Thermal Characteristics
Symbol
R
胃JC
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink Typ.
Typ
--
--
Max
4.2
110
Unit
擄C/W
擄C/W
漏2007 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FDD3N40 / FDU3N40 Rev. A