鈥?/div>
51A, 250V, R
DS(on)
= 0.06惟 @V
GS
= 10 V
Low gate charge ( typical 55 nC)
Low Crss ( typical 63 pF)
Fast switching
Improved dv/dt capability
UniFET
TM
July 2008
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild鈥檚 proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies and active power factor
correction.
D
G
G DS
TO-220
FDP Series
GD S
TO-220F
FDPF Series
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J,
T
STG
T
L
Drain-Source Voltage
Drain Current
Drain Current
Gate-Source voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
(T
C
= 25擄C)
- Derate above 25擄C
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Parameter
- Continuous (T
C
= 25擄C)
- Continuous (T
C
= 100擄C)
- Pulsed
(Note 1)
FDP51N25
51
30
204
FDPF51N25
250
51*
30*
204*
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
鹵
30
1111
51
32
4.5
320
3.7
-55 to +150
300
38
0.3
W
W/擄C
擄C
擄C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purpose,
1/8鈥?from Case for 5 Seconds
*Drain current limited by maximum junction temperature
Thermal Characteristics
Symbol
R
胃JC
R
胃CS
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink Typ.
Thermal Resistance, Junction-to-Ambient
FDP51N25
0.39
0.5
62.5
FDPF51N25
3.3
--
62.5
Unit
擄C/W
擄C/W
擄C/WJ
漏2008 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FDP51N25 / FDPF51N25 Rev. B