鈩?/div>
@V
GS
= 10 V
Low gate charge ( typical 30 nC)
Low Crss ( typical 60 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
TM
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild鈥檚 proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies, active power factor
correction, electronic lamp ballast based on half bridge
topology.
D
G
G DS
TO-220
FDP Series
GD S
TO-220F
FDPF Series
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
T
C
= 25擄C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (T
C
= 25擄C)
Drain Current
- Continuous (T
C
= 100擄C)
Drain Current
- Pulsed
(Note 1)
FDP55N06
60
55
34.8
220
鹵
25
(Note 2)
(Note 1)
(Note 1)
(Note 3)
FDPF55N06
55 *
34.8 *
220 *
480
55
11.4
4.5
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/擄C
擄C
擄C
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
C
= 25擄C)
- Derate above 25擄C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8鈭€ from case for 5 seconds
114
0.9
-55 to +150
300
48
0.4
* Drain current limited by maximum junction temperature
Thermal Characteristics
Symbol
R
胃JC
R
胃JS
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink Typ.
Thermal Resistance, Junction-to-Ambient
FDP55N06
1.1
0.5
62.5
FDPF55N06
2.58
--
62.5
Units
擄C/W
擄C/W
擄C/W
漏2005 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FDP55N06/FDPF55N06 Rev. A