May 1998
FDC636P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as cellular phone and
notebook computer power management and other battery
powered circuits where high-side switching, and low in-line
power loss are needed in a very small outline surface
mount package.
Features
-2.8 A, -20 V. R
DS(ON)
= 0.130
鈩?/div>
@ V
GS
= -4.5 V
R
DS(ON)
= 0.180
鈩?/div>
@ V
GS
= -2.5 V.
SuperSOT
TM
-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOT -6
TM
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
S
D
D
1
6
.63
6
2
5
G
SuperSOT
TM
pin
1
D
D
3
4
-6
Absolute Maximum Ratings
T
A
= 25擄C unless otherwise noted
Symbol Parameter
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1a)
FDC636P
-20
鹵8
-2.8
-11
1.6
0.8
-55 to 150
Units
V
V
A
W
T
J
,T
STG
R
胃JA
R
胃JC
Operating and Storage Temperature Range
擄C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
30
擄C/W
擄C/W
漏 1998 Fairchild Semiconductor Corporation
FDC636P Rev.B
1
2
3
4
