March 1998
FDC633N
N-Channel Enhancement Mode Field Effect Transistor
General Description
This N-Channel enhancement mode power field effect
transistors is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMICA cards, and other
battery powered circuits where fast switching,low in-line
power loss and resistance to transients are needed in a very
small outline surface mount package.
Features
5.2 A, 30 V. R
DS(ON)
= 0.042
鈩?/div>
@ V
GS
= 4.5 V
R
DS(ON)
= 0.054
鈩?/div>
@ V
GS
= 2.5 V.
SuperSOT
TM
-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOT -6
TM
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
S
D
D
1
6
.63
3
2
5
G
SuperSOT
TM
pin
1
D
D
3
4
-6
Absolute Maximum Ratings
T
A
= 25擄C unless otherwise noted
Symbol Parameter
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1a)
FDC633N
30
鹵8
5.2
16
1.6
0.8
-55 to 150
Units
V
V
A
W
T
J
,T
STG
R
胃JA
R
胃JC
Operating and Storage Temperature Range
擄C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
30
擄C/W
擄C/W
漏 1998 Fairchild Semiconductor Corporation
FDC633N Rev.C
1
2
3
4
