FDC6333C
October 2001
FDC6333C
30V N & P-Channel PowerTrench
廬
MOSFETs
General Description
These N & P-Channel MOSFETs are produced using
Fairchild Semiconductor鈥檚 advanced PowerTrench
process that has been especially tailored to minimize
on-state resistance and yet maintain superior
switching performance.
These devices have been designed to offer
exceptional power dissipation in a very small footprint
for applications where the bigger more expensive
SO-8 and TSSOP-8 packages are impractical.
Features
鈥?/div>
Q1
2.5 A, 30V.
R
DS(ON)
= 95 m鈩?@ V
GS
= 10 V
R
DS(ON)
= 150 m鈩?@ V
GS
= 4.5 V
鈥?/div>
Q2
鈥?.0 A, 30V.
R
DS(ON)
= 150 m鈩?@ V
GS
= 鈥?0 V
R
DS(ON)
= 220 m鈩?@ V
GS
= 鈥?.5 V
鈥?/div>
Low gate charge
鈥?/div>
High performance trench technology for extremely
low R
DS(ON)
.
鈥?/div>
SuperSOT 鈥? package: small footprint (72% smaller than
SO-8); low profile (1mm thick).
Applications
鈥?/div>
DC/DC converter
鈥?/div>
Load switch
鈥?/div>
LCD display inverter
D2
S1
D1
Q2(P)
4
G2
3
2
1
Q1(N)
5
6
SuperSOT
TM
-6
Pin 1
S2
G1
SuperSOT鈩?6
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current
鈥?Continuous
鈥?Pulsed
T
A
=25 C unless otherwise noted
o
Parameter
Q1
30
鹵16
(Note 1a)
Q2
鈥?0
鹵25
鈥?.0
鈥?
0.96
0.9
0.7
鈥?5 to +150
Units
V
V
A
2.5
8
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
W
擄C
T
J
, T
STG
Operating and Storage Junction Temperature Range
Thermal Characteristics
R
胃JA
R
胃JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
130
60
擄C/W
擄C/W
Package Marking and Ordering Information
Device Marking
.333
Device
FDC6333C
Reel Size
7鈥欌€?/div>
Tape width
8mm
Quantity
3000 units
漏2001
Fairchild Semiconductor Corporation
FDC6333C Rev C (W)
FDC6333C相關(guān)型號PDF文件下載
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