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FDC6304P Datasheet

  • FDC6304P

  • Digital FET, Dual P-Channel

  • 77.37KB

  • 4頁(yè)

  • FAIRCHILD

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July 1997
FDC6304P
Digital FET, Dual P-Channel
General Description
These P-Channel enhancement mode field effect transistor are
produced using Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is tailored to minimize
on-state resistance at low gate drive conditions. This device is
designed especially for application in battery power applications
such as notebook computers and cellular phones. This device
has excellent on-state resistance even at gate drive voltages as
low as 2.5 volts.
Features
-25 V, -0.46 A continuous, -1.0 A Peak.
R
DS(ON)
= 1.5
鈩?/div>
@ V
GS
= -2.7 V
R
DS(ON)
= 1.1
鈩?/div>
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.
SOT-23
SuperSOT -6
Mark: .304
TM
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
4
3
5
2
6
1
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
ESD
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current
T
A
= 25
o
C unless other wise noted
FDC6304P
-25
-8
Units
V
V
A
- Continuous
- Pulsed
-0.46
-1
(Note 1a)
(Note 1b)
Maximum Power Dissipation
0.9
0.7
-55 to 150
6.0
W
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
擄C
kV
THERMAL CHARACTERISTICS
R
JA
R
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
140
60
擄C/W
擄C/W
FDC6304P Rev.D
漏 1997 Fairchild Semiconductor Corporation

FDC6304P 產(chǎn)品屬性

  • High Voltage Switches for Power Processing

  • 3,000

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 陣列

  • -

  • 2 個(gè) P 溝道(雙)

  • 邏輯電平門

  • 25V

  • 460mA

  • 1.1 歐姆 @ 500mA,4.5V

  • 1.5V @ 250µA

  • 1.5nC @ 4.5V

  • 62pF @ 10V

  • 700mW

  • 表面貼裝

  • SOT-23-6 細(xì)型,TSOT-23-6

  • 6-SSOT

  • 帶卷 (TR)

  • FDC6304P-NDFDC6304PTR

FDC6304P相關(guān)型號(hào)PDF文件下載

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