August 1997
FDC6303N
Digital FET, Dual N-Channel
General Description
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. This device has been designed especially for
low voltage applications as a replacement for digital
transistors in load switching applications. Since bias
resistors are not required this one N-Channel FET can
replace several digital transistors with different bias
resistors like the IMHxA series.
Features
25 V, 0.68 A continuous, 2 A Peak.
R
DS(ON)
= 0.6
鈩?/div>
@ V
GS
= 2.7 V
R
DS(ON)
= 0.45
鈩?/div>
@ V
GS
= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple NPN digital transistors (IMHxA series)
with one DMOS FET.
SOT-23
SuperSOT
TM
-6
SuperSOT -8
TM
SO-8
SOT-223
SOIC-16
Mark: .303
4
3
5
2
6
1
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
ESD
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current
T
A
= 25擄C unless otherwise noted
FDC6303N
25
8
- Continuous
- Pulsed
0.68
2
(Note 1a)
(Note 1b)
Units
V
V
A
Maximum Power Dissipation
0.9
0.7
-55 to 150
6.0
W
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
擄C
kV
THERMAL CHARACTERISTICS
R
胃
JA
R
胃
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
140
60
擄C/W
擄C/W
漏 1997 Fairchild Semiconductor Corporation
FDC6303N Rev.C
next