April 1998
FDP6035L/FDB6035L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as DC/DC converters and
high efficiency switching circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
Features
58 A, 30 V. R
DS(ON)
= 0.011
鈩?/div>
@ V
GS
=10 V
R
DS(ON)
= 0.019
鈩?/div>
@ V
GS
=4.5 V
.
Low gate charge (typical 34 nC).
Low Crss (typical 175 pF).
Fast switching speed.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
T
C
= 25擄C unless otherwise noted
FDP6035L
30
鹵20
58
175
75
0.5
-65 to 175
FDB6035L
Units
V
V
A
Maximum Power Dissipation @ T
C
= 25擄C
Derate above 25擄C
W
W/擄C
擄C
T
J
,T
STG
R
胃
JC
R
胃JA
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
2
62.5
擄C/W
擄C/W
漏 1998 Fairchild Semiconductor Corporation
FDP6035L Rev.B
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