鈥?/div>
Pull-up resistor on I/O pins during in鈥搒ystem programming
High鈥揹ensity PLDs ranging from 600 to 10,000 usable gates
4.5鈥搉s pin鈥搕o鈥損in logic delays with counter frequencies of up to
227.3 MHz
MultiVolt
TM
I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0鈥揤, 3.3鈥揤, and 2.5鈥揤 logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J鈥搇ead chip carrier
(PLCC), and FineLine BGA
TM
packages
Hot鈥搒ocketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Industrial temperature range
Table 1. MAX 3000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
PD
(ns)
t
SU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
Altera Corporation
DS-MAX3000A-3.5
EPM3032A
600
32
2
34
4.5
2.9
3.0
227.3
EPM3064A
1,250
64
4
66
4.5
2.8
3.1
222.2
EPM3128A
2,500
128
8
98
5.0
3.3
3.4
192.3
EPM3256A
5,000
256
16
161
7.5
5.2
4.8
126.6
EPM3512A
10,000
512
32
208
7.5
5.6
4.7
116.3
1