音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

EP1C12F256I7N Datasheet

  • EP1C12F256I7N

  • CYCLONE FPGA 12K, SMD, 1C12F256; Programmable Logic Type:FPG...

  • 1359.00KB

  • 104頁(yè)

  • Altera   Altera

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

Cyclone
廬
FPGA Family
Data Sheet
March 2003, ver. 1.1
Introduction
Preliminary
Information
The Cyclone
TM
field programmable gate array family is based on a 1.5-V,
0.13-碌m, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Features...
2,910 to 20,060 LEs, see
Table 1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
Altera
錚?/div>
MegaCore
錚?/div>
functions and Altera Megafunctions Partners
Program (AMPP
SM
) megafunctions
Table 1. Cyclone Device Features
Feature
LEs
M4K RAM blocks (128
脳
36 bits)
Total RAM bits
PLLs
Maximum user I/O pins
(1)
Note to
Table 1:
(1)
This parameter includes global clock pins.
EP1C3
2,910
13
59,904
1
104
EP1C4
4,000
17
78,336
2
301
EP1C6
5,980
20
92,160
2
185
EP1C12
12,060
52
239,616
2
249
EP1C20
20,060
64
294,912
2
301
Altera Corporation
DS-CYCLONE-1.1
1

EP1C12F256I7N 產(chǎn)品屬性

  • Three Reasons to Use FPGA's in Industrial Designs

  • 90

  • 集成電路 (IC)

  • 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列）

  • Cyclone®

  • 1206

  • 12060

  • 239616

  • 185

  • -

  • 1.425 V ~ 1.575 V

  • 表面貼裝

  • -40°C ~ 100°C

  • 256-BGA

  • 256-FBGA（17x17）

  • 544-1676

EP1C12F256I7N相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買(mǎi)家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！