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EBE20RE4AAFA Datasheet

  • EBE20RE4AAFA

  • 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank...

  • 22頁

  • ELPIDA

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DATA SHEET
2GB Registered DDR2 SDRAM DIMM
EBE20RE4AAFA
(256M words
脳
72 bits, 1 Rank)
Description
The EBE20RE4AAFA is a 256M words
脳
72 bits, 1
rank DDR2 SDRAM Module, mounting 18 pieces of
DDR2 SDRAM sealed in FBGA (碌BGA
錚?/div>
) package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 4bits prefetch-pipelined
architecture. Data strobe (DQS and /DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA
(碌BGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
鈥?/div>
240-pin socket type dual in line memory module
(DIMM)
錚?/div>
PCB height: 30.0mm
錚?/div>
Lead pitch: 1.0mm
錚?/div>
Lead-free
鈥?/div>
Power supply: VDD, VDDQ
=
1.8V
鹵
0.1V
鈥?/div>
Data rate: 533Mbps/400Mbps (max.)
鈥?/div>
SSTL_18 compatible I/O
鈥?/div>
Double-data-rate architecture: two data transfers per
clock cycle
鈥?/div>
Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
鈥?/div>
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
鈥?/div>
Differential clock inputs (CK and /CK)
鈥?/div>
DLL aligns DQ and DQS transitions with CK
transitions
鈥?/div>
Commands entered on each positive CK edge; data
referenced to both edges of DQS
鈥?/div>
Eight internal banks for concurrent operation
(Component)
鈥?/div>
Burst length: 4, 8
鈥?/div>
/CAS latency (CL): 3, 4, 5
鈥?/div>
Auto precharge option for each burst access
鈥?/div>
Auto refresh and self refresh modes
鈥?/div>
Average refresh period
錚?/div>
7.8碌s at 0擄C
鈮?/div>
TC
鈮?+85擄C
錚?/div>
3.9碌s at
+85擄C <
TC
鈮?+95擄C
鈥?/div>
Posted CAS by programmable additive latency for
better command and data bus efficiency
鈥?/div>
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
鈥?/div>
/DQS can be disabled for single-ended Data Strobe
operation
鈥?/div>
1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
Document No. E0440E30 (Ver. 3.0)
Date Published March 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
錚〦lpida
Memory, Inc. 2003-2005

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