Edge720
500 MHz Pin Electronics Driver,
Window Comparator, and Load
TEST AND MEASUREMENT PRODUCTS
Description
The Edge720 is a totally monolithic ATE pin electronics
solution manufactured in a high-performance
complementary bipolar process.
The three-statable driver is capable of generating 9V
swings over a 鈥?V to +12V range. In addition, 13V super
voltage may be obtained under certain operating
conditions. An input power down mode allows extremely
low leakage current in HiZ. Thus, the Edge720 can help
to eliminate relays that are typically used to isolate devices
such as per pin measurement units from the driver/
comparator/load.
The load supports programmable source and sink currents
of
鹵
35 mA over a 鈥?V to +12V range, or it can be
completely disabled. In addition, the load is configurable
and may be used as a programmable voltage clamp.
The window comparator spans a 13V common mode
range, tracks input signals with edge rates greater than 6
V/ns and passes sub-ns pulses. An input power down
mode allows for extremely low leakage measurements.
The inclusion of all pin electronics building blocks into a
52 lead QFP (10 mm body w/ exposed heat sink) offers a
highly integrated solution that is traditionally implemented
with multiple integrated circuits or discretes.
The Edge720 is a variant of the Edge710, with the
following improvements:
鈥?Reduced D+C+L Leakage Current
鈥?Increased Super Voltage Range
鈥?Additional VCM_IN buffer reduces the need for
an external buffer when using the load circuit as
a programmable clamp.
Features
鈥?Fully Integrated Three-Statable Driver, Window
Comparator, and Dynamic Active Load
鈥?13V Driver, Load, Compare Range
鈥?+13V Super Voltage Capable
鈥?/div>
鹵
35 mA Programmable Load
鈥?Comparator Input Tracking >6V/ns
鈥?Leakage (L+D+C) < 2
碌A(chǔ)
(normal mode, typical)
鈥?Leakage (L+D+C) < 30 nA (power-down mode,
guaranteed)
鈥?Small footprint (52 lead Exposed Pad QFP)
Applications
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Flash Memory Test
VLSI Test Equipment
Mixed-Signal Test Equipment
Memory Testers (Bidirectional Channels)
ASIC Verifiers
Functional Block Diagram
BIAS
DVH
DVH_CAP
RADJ
DOUT
DVR_EN
DVR_EN*
FADJ
DVL_CAP
DHI
DHI*
DVL
IPD_D
QA*
QA
IPD_C
SUPERV
PECL
QB
QB*
CVA
VINP
CVB
VCC
ISC
ISC_IN
VCM_IN_A
VCM_OUT_A
VCM_IN_B
VCM_OUT_B
ISK_IN
LD_EN
LD_EN*
BRIDGE_SC
LOAD
BRIDGE_SK
ISK
VEE
Revision 4 / October 3, 2002
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