Edge629
1 GHz Timing Deskew and
Quad Fanout Element
HIGH-PERFORMANCE PRODUCTS 鈥?ATE
Description
The Edge629 is a monolithic timing delay and signal
fanout solution manufactured in a high-performance
bipolar process. In Automatic Test Equipment (ATE)
applications, the Edge629 buffers, distributes, and aligns
timing signals across multiple channels (typically found
inside Memory Test Systems). It is also suitable for per
pin deskew in Logic Testers.
The Edge629 supports:
鈥?Minimum pulse width = 330 ps with Falling
Edge Adjust disabled, 500 ps with Falling
Edge Adjust enabled
鈥?Net usable delay span
鈮?/div>
4.0 ns
鈥?Falling Edge Adjust
鹵250
ps
鈥?On Board DACs to generate 5 ps minimum
resolution.
With a maximum operating frequency of 1 GHz, the
Edge629 is optimized for extremely high speed, high
accuracy testers, particularly those aimed to test
RAMBUS memory devices.
The Edge629 solves several difficult problems
associated with aligning multiple timing signals because
it can:
鈥?delay very narrow pulses over a long
timing span
鈥?adjust the falling edge independently from the overall
propagation delay
鈥?maintain extreme timing accuracy for very narrow
(sub-ns) pulses
鈥?maintain tight timing accuracy over changes in
frequency, duty cycle, and pattern.
TARGET
Featur es
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fmax
鈮?/div>
1 GHz
Independent Falling Edge Adjust
Small Footprint (10 mm x 10 mm)
Excellent Timing Accuracy
Very Stable Timing Delays
5 ps Minimum Resolution
ECL, CMOS Compatible Inputs
Functional Block Diagram
IN0 / IN0*
鈭員鈥?/div>
鈭員
Coarse
鈭員
Fine
OUT0 / OUT0*
IN / IN*
IN1/ IN1*
鈭員鈥?/div>
鈭員
Coarse
鈭員
Fine
OUT1 / OUT1*
IN2 / IN2*
鈭員鈥?/div>
鈭員
Coarse
鈭員
Fine
OUT2 / OUT2*
Applications
鈥?/div>
Memory Test Equipment
鈥?Data Fanout
鈥?Channel Deskew
Logic Testers
鈥?Per Pin Deskew
Clock / Signal Fanout
IN3 / IN3*
鈭員鈥?/div>
鈭員
Coarse
鈭員
Fine
OUT3 / OUT3*
鈥?/div>
鈥?/div>
SEL / SEL*
Revision 1 / Febr uar y 13, 2002
1
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