鈩?/div>
-DT are the latest offerings in
the DVx family of products. DVxcel-LE is designed to enable very low-cost
video peripherals, based on MPEG-1 and MPEG-2 compression standards for
archiving and web-streaming applications. The DVxcel-VC, a single-chip
MPEG-2 codec capable of encoding and decoding video simultaneously,
is targeted at the emerging time-shift and digital video recording (DVR)
applications. The DVxcel-DT includes the same functionality and features as
the DVxcel-VC, with additional support for DV encode and decode as well
as transcoding from DV to MPEG-2; features that are critical for enabling
new video editing applications. All support both NTSC and PAL formats.
Based on LSI Logic鈥檚 fourth-generation video processor architecture,
these devices are optimized, both in hardware design and functionality, for
high-quality, low-cost video-centric consumer applications. Using LSI Logic鈥檚
proven PerfectView
廬
encoding algorithm, this product family delivers the
highest quality video encoding with the lowest bit rate of any consumer-based
solution.
FEATURES:
鈥?Flexible 16/32-bit host interface
鈥?Host DMA target or primary 8-bit
HW I/O ports for bitstream data
transfers
鈥?Secondary 8-bit hardware port for
bitstream
鈥?Tertiary 8-bit hardware port for bit-
stream transfer
鈥?8/10-bit ITU-656 video input port
鈥?8-bit ITU-656/601 video output port
(not available with DVxcel-LE)
鈥?Serial audio interface for audio cap-
ture and playback
All the DVxcel devices utilize special
hardware to implement the following
algorithmic functions:
TARGET APPLICATIONS
Web Sharing
Today an extensive amount of multimedia content is available on the
Web. As digital subscriber line (DSL) and cable modems become more popu-
lar, the need for high-quality, low bit rate video is increasing. The DVxcel鈥檚
sophisticated MPEG-1 and -2 compression algorithms provide superior quality
and can accommodate bit rates as low as 384 Kbps. Video compression is
critical for Web sharing and distribution where file size is important.
MicroSPARC
陋
Core
鈥?Video compression pre-processing
鈥?Motion estimation and compensation
2
PIO
鈥?DCTs and IDCTs
鈥?Variable-length encoding and decoding
10
Motion
Video DSP
Video
Interface
text
Estimator
Audio
Interface
4
4
鈥?High-quality video scaling and com-
posting
16/32
HOST
Interface/
Secondary
BSIO
Tertiary
BSIO
SDRAM
Controller
64
8
Shared with upper
16bit of host interface
Primary/
BSIO
8
8
8
8
The
Communications
Company
TM
DVxcel
鈩?/div>
Internal Block Diagram
1
2
3
4
