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DT70V27S Datasheet

  • DT70V27S

  • HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM

  • 192.75KB

  • 22頁

  • IDT

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HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
Features:
x
x
x
IDT70V27S/L
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
鈥?Industrial: 35ns (max.)
鈥?Commercial: 15/20/25/35/55ns (max.)
Low-power operation
鈥?IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
鈥?IDT70V27L
Active: 500mW (typ.)
Standby: 660
碌
W (typ.)
Separate upper-byte and lower-byte control for bus
matching capability
Dual chip enables allow for depth expansion without
external logic
x
x
x
x
x
x
x
x
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (鹵0.3V) power supply
Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA
(fpBGA)
Industrial temperature range (-40擄C to +85擄C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/W
R
UB
R
CE
0R
CE
1L
OE
L
LB
L
CE
1R
OE
R
LB
R
I/O
8-15L
I/O
0-7L
BUSY
L
(1,2)
I/O
Control
I/O
Control
I/O
8-15R
I/O
0-7R
BUSY
R
(1,2)
A
14L
A
0L
Address
Decoder
A
14L
A
0L
CE
0L
32Kx16
MEMORY
ARRAY
70V27
Address
Decoder
A
14R
A
0R
CE
1L
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
14R
A
0R
CE
0R
CE
1R
OE
R
R/
W
L
SEM
L
INT
L
(2)
R/
W
R
SEM
R
NOTES:
1)
BUSY
is an input as a Slave (M/S=V
IL
) and an output as a Master (M/S=V
IH
).
2)
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
M/
S
(2)
INT
R
3603 drw 01
(2)
JANUARY 2001
6.01
1
漏2000 Integrated Device Technology, Inc.
DSC 3603/7

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