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DSP96002RC60 Datasheet

  • DSP96002RC60

  • 32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSOR

  • 111頁

  • MOTOROLA   MOTOROLA

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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document by:
DSP96002/D, Rev. 2
DSP96002
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT
PROCESSOR
The DSP96002 is designed to support intensive graphic image and numeric processing. It is
a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024
words of data RAM (equally divided into X data and Y data memory), 1024 words of full-
speed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA)
controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE鈩? debug
circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units
operating in parallel. The DSP96002 has two identical memory expansion ports with control
lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and
Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which
facilitates easy interface with other processors for multiprocessor applications. Linear arrays
of DSP96002s can be implemented without glue logic. The MPU-style programming model
and instruction set allow straightforward generation of efficient, compact code. The high
speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive
applications that require floating-point processing and access to large memory subsystems.
Control
18
Control
18
Freescale Semiconductor, Inc...
Bus
Control
Address
Generation
Unit (AGU)
YAB *
XAB *
PAB *
Program *
X Data *
Memory
Memory
1024
脳
32 512
脳
32
RAM and
RAM
64
脳
32
Bootstrap
512
脳
32鈥?/div>
ROM
ROM
Instruction
Cache
DDB
YDB
XDB
PDB
GDB
Y Data *
Memory
512
脳
32
RAM
512
脳
32鈥?/div>
ROM
Bus
Control
Address
External
32
Address
Switch
Dual Channel
DMA
Controller
Internal
Switch And Bit
Manipulation
Unit
External Address
32
Address
Switch
4
Port B
32
Data
AA0306
Port A
4
32-bit
Host
Interface
Timer
External
Data
Bus
Switch
32-bit
Host
Interface
Timer
External
Data
Bus
Switch
32
Data
Clock
Generator
Program
Decode
Controller
Program
Address
Generator
Program Controller
Program
Interrupt
Controller
OnCE
Data ALU
Debug
鈥?IEEE Floating Point Controller
鈥?32
脳
32 Integer ALU
4
Serial Debug
Port
CLK
32-bit Buses
* Dual Access (DMA/Core)
鈥?1024
脳
32 Virtual Locations
MODC/IRQC
MODB/IRQB
MODA/IRQA
RESET
Figure 1
Block Diagram
漏1996 MOTOROLA, INC.
For More Information On This Product,
Go to: www.freescale.com

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