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DSP56300FM/AD Datasheet

  • DSP56300FM/AD

  • high density CMOS device with 3.3 V inputs and outputs

  • 128頁(yè)

  • MOTOROLA   MOTOROLA

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Freescale Semiconductor
Technical Data
DSP56374
Rev. 1, 11/2004
Overview
The DSP56374 is a high density CMOS device with 3.3 V inputs and outputs.
NOTE
This document contains information on a new product.
Specifications and information herein are subject to
change without notice.
Finalized specifications may be published after further characterization and device
qualifications are completed.
The DSP56374 supports digital audio applications requiring sound field processing,
acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high
performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital
signal processors (DSPs) combined with the audio signal processing capability of the
Freescale Semiconductor, Inc. (formerly Motorola) Symphony鈩?DSP family, as shown in
Figure 1.
Significant architectural enhancements include a barrel shifter, 24-bit addressing,
and direct memory access (DMA). The DSP56374 offers 150 million instructions per second
(MIPS) using an internal 150 MHz clock.
Table of Contents
Section
Page
1 Features........................................ 2
2 Documentation.............................. 4
3 Signal Groupings .......................... 4
4 Maximum Ratings ....................... 24
5 Power Requirements................... 25
6 Thermal Characteristics.............. 26
7 DC Electrical Characteristics ...... 26
8 AC Electrical Characteristics....... 27
9 Internal Clocks ............................ 27
10 External Clock Operation .......... 29
11 Reset, Stop, Mode Select, and
Interrupt Timing ........................... 30
12 Serial Host Interface SPI Protocol
Timing.......................................... 34
13 Serial Host Interface (SHI) I2C
Protocol Timing ........................... 40
14 Programming the Serial Clock .. 42
15 Enhanced Serial Audio Interface
Timing.......................................... 43
16 Timer Timing ............................. 48
17 GPIO Timing ............................. 48
18 JTAG Timing ............................. 50
19 Watchdog Timer Timing ............ 52
Appendix A Package Information. 53
Appendix B IBIS Model ................. 63
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
鈥渁sserted鈥?/div>
Used to indicate a signal that is active when pulled low (For
example, the RESET pin is active when low.)
Means that a high true (active high) signal is high or that a low true
(active low) signal is low
鈥渄easserted鈥?Means that a high true (active high) signal is low or that a low true
(active low) signal is high
Examples:
Signal/
Symbol
PIN
PIN
PIN
PIN
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage*
V
IL
/ V
OL
V
IH
/ V
OH
V
IH
/ V
OH
V
IL
/ V
OL
Note:
*Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
漏 Freescale Semiconductor, Inc., 2004. All rights reserved.
PRELIMINARY

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