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DSP56166 Datasheet

  • DSP56166

  • 16-bit General Purpose Digital Signal Processor

  • 439.95KB

  • 63頁

  • MOTOROLA   MOTOROLA

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Advance Information
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Order this document
by DSP56166/D
DSP56166
Ceramic Quad Flat Pack (CQFP)
Available in a 112 pin, small footprint,
surface mount package.
16-bit General Purpose
Digital Signal Processor
The DSP56166 is the second member of Motorola鈥檚 DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal
Processors (DSP). Designed primarily for speech coding and digital communications, the DSP56166 has a built-in
危鈭?/div>
codec and
phase locked loop (PLL). This MPU-style DSP also contains, memories, digital peripherals, and provides a cost effective, high per-
formance solution to many DSP applications. On-Chip Emulation (OnCE
鈩?/div>
) circuitry provides convenient and inexpensive debug fa-
cilities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly
simplified by using the OnCE. The DSP56166 RAM based is an off the shelf part since there are no user programmable ROM鈥檚 on-
chip. The DSP56166 ROM based contains a 12K ROM (8Kx 16 program ROM and 4Kx16 data ROM).
The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an
instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56166. The MPU-style programming
model and instruction set allow straightforward generation of efficient, compact code. The basic architectures and development tools
of the DSP56100 family, DSP56000 family, and DSP96002 are so similar that learning to design and program one greatly reduces
the time needed to learn the others.
DSP56166ROM Feature List
DSP56100 Family Features
鈥?Up to 30 Million Instructions per Second (MIPS) at 60
MHz.鈥?33.3 ns Instruction cycle
鈥?Single-cycle 16 x 16-bit parallel Multiply-Accumulate
鈥?2 x 40-bit accumulators with extension byte
鈥?Fractional and integer arithmetic with support for
multiprecision arithmetic
鈥?Highly parallel instruction set with unique DSP
addressing modes
鈥?Nested hardware DO loops including infinite loops and
DO zero loop
鈥?Two instruction LMS adaptive filter loop
鈥?Fast auto-return interrupts
鈥?Three external interrupt request pins
鈥?Three 16-bit internal data and three 16-bit internal
address buses
鈥?Individual programmable wait states on the external bus
for program, data, and peripheral memory spaces
鈥?Off-chip memory-mapped peripheral space with
programmable access time and separate peripheral
enable pin
鈥?On-chip memory-mapped peripheral registers
鈥?Low Power Wait and Stop modes
鈥?On-Chip Emulation (OnCE
)
for unobtrusive, processor
speed independent debugging
鈥?Operating frequency down to DC
鈥?5V single power supply
鈥?Low power (HCMOS)
DSP56166ROM On-chip Resources
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
4K x 16 on-chip data RAM
4K x 16 on-chip data ROM
256 x 16 on-chip program RAM
8K x 16 on-chip program ROM
One external 16-bit address bus
One external 16-bit data bus
On-chip
危鈭?/div>
voice band codec (A/D-D/A)
鈥?Internal voltage reference (2/5 of positive power
supply)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?No off-chip components required
25 general purpose I/O pins
On-chip, programmable PLL
Byte-wide Host Interface with DMA support
Two independent reduced synchronous serial
interfaces
One 16-bit timer
112 pin quad flat pack packaging
Operational Differences Of The ROM Based Part From The RAM Based Part
鈥?XROM can only be accessed during a single read or the
first read of a dual parallel read instruction (see note on
page 2)
鈥?Reset mode 1 vectors to P:$0100
鈥?PROM area P:$2080 鈥?P:$20FF is reserved and
should not be programmed or accessed by the user
This document contains information on a new product. Speci鏗乧ations and information herein are subject to change without notice.
MOTOROLA
漏
MOTOROLA INC., 1993
6/15/93

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