DSP1629 Datasheet

IC型號：
DSP1629
PDF描述：
DSP1629 Digital Signal Processor
文件大小：
1830.30KB
PDF頁數(shù)：
126頁
芯片廠家：
AGERE

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Data Sheet

March 2000

DSP1629 Digital Signal Processor

1 Features

Optimized for digital cellular applications with a bit

manipulation unit for higher coding efficiency.

On-chip, programmable, PLL clock synthesizer.

10 ns and 16.7 ns instruction cycle times at 3.0 V, and

19.2 ns and 12.5 ns instruction cycle times at 2.7 V,

respectively.

Mask-programmable memory map option: The

DSP1629x16 features 16 Kwords on-chip dual-port

RAM. The DSP1629x10 features 10 Kwords on-chip

dual-port RAM. Both feature 48 Kwords on-chip ROM

with a secure option.

Low power consumption:

鈥?<1.9 mW/MIPS typical at 2.7 V.

Flexible power management modes:

鈥?Standard sleep: 0.2 mW/MIPS at 2.7 V.

鈥?Sleep with slow internal clock: 0.7 mW at 2.7 V.

鈥?Hardware STOP (pin halts DSP): <20

碌A.

Mask-programmable clock options: small signal, and

CMOS.

144 PBGA package (13 mm x 13 mm) available.

Sequenced accesses to X and Y external memory.

Object code and pin compatible with the DSP1627.

Single-cycle squaring.

16 x 16-bit multiplication and 36-bit accumulation in

one instruction cycle.

Instruction cache for high-speed, program-efficient,

zero-overhead looping.

Dual 25 Mbits/s serial I/O ports with multiprocessor

capability:

鈥?16-bit data channel, 8-bit protocol channel.

8-bit parallel host interface:

鈥?Supports 8- or 16-bit transfers.

鈥?/div>

Motorola

Intel

鈥?/div>

compatible.

8-bit control I/O interface.

256 memory-mapped I/O ports.

Full-speed in-circuit emulation hardware develop-

ment system on-chip.

Supported by DSP1629 software and hardware

development tools.

2 Description

The DSP1629 is Lucent Technologies Microelectronics

Group鈥檚 first digital signal processor offering 100 MIPS

operation at 3.0 V and 80 MIPS operation at 2.7 V with a

reduction in power consumption. Designed specifically

for applications requiring low power dissipation in digital

cellular systems, the DSP1629 is a signal-coding device

that can be programmed to perform a wide variety of

fixed-point signal processing functions. The device is

based on the DSP1600 core with a bit manipulation unit

for enhanced signal coding efficiency. The DSP1629 in-

cludes a mix of peripherals specifically intended to sup-

port processing-intensive but cost-sensitive applications

in the area of digital wireless communications.

The DSP1629x16 contains 16 Kwords of internal dual-

port RAM (DPRAM), which allows simultaneous access

to two RAM locations in a single instruction cycle. The

DSP1629x10 supports the use of 10 Kwords of DPRAM.

Both devices contain 48 Kwords of internal ROM (IROM).

The DSP1629 is object code compatible with the

DSP1627 while providing more memory. The DSP1629 is

pin compatible with the DSP1627. Note that TRST (JTAG

test reset) replaces a V

pin.

The DSP1629 supports 2.7 V, and 3.0 V operation and

flexible power management modes required for portable

cellular terminals. Several control mechanisms achieve

low-power operation, including a STOP pin for placing the

DSP into a fully static, halted state and a programmable

power control register used to power down unused on-

chip I/O units. These power management modes allow

for trade-offs between power reduction and wake-up la-

tency requirements. During system standby, power con-

sumption is reduced to less than 20

碌A.

The on-chip clock synthesizer can be driven by an exter-

nal clock whose frequency is a fraction of the instruction

rate.

The device is packaged in a 144-pin PBGA, a 100-pin

BQFP, or a 100-pin TQFP and is available with 10 ns and

16.7 ns instruction cycle times at 3.0 V, and 19.2 ns and

12.5 ns instruction cycle times at 2.7 V, respectively.

IEEE

鈥?/div>

P1149.1 test port (JTAG boundary scan).

Motorola

is a registered trademark of Motorola, Inc.

鈥?/div>

Intel

is a registered trademark of Intel Corporation.

鈥?/div>

IEEE

is a registered trademark of The Institute of Electrical

and Electronics Engineers, Inc.

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