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DSP16210 Datasheet

  • DSP16210

  • DSP16210 Digital Signal Processor

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  • 173頁(yè)

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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Features
s
Description
The DSP16210 is the first DSP device based on the
DSP16000 digital signal processing core. It is manufactured
in a 0.35
碌m
CMOS technology and offers a 10 ns instruc-
tion cycle time at 3 V operation. Designed specifically for
applications requiring a large amount of memory, a flexible
DMA-based I/O structure, and high cycle efficiency, the
DSP16210 is a signal coding device that can be pro-
grammed to perform a wide variety of fixed-point signal pro-
cessing functions. The DSP16210 includes a mix of
peripherals specifically intended to support processing-
intensive but cost-sensitive applications.
The large on-chip RAM (60 Kwords of dual-port RAM) sup-
ports downloadable system design鈥攁 must for infrastruc-
ture applications鈥攖o support field upgrades for evolving
coding standards. The DSP16210 can address up to
192 Kwords of external storage in both its code/coefficient
memory address space and data memory address space.
In addition, there is an internal boot ROM (IROM) that
includes system boot code and hardware development sys-
tem (HDS) code.
This device also contains a bit manipulation unit (BMU) and
a two-input, 40-bit arithmetic logic unit (ALU) with add/com-
pare/select (ACS) for enhanced signal coding efficiency
and Viterbi acceleration.
To optimize I/O throughput and reduce the I/O service rou-
tine burden on the DSP core, the DSP16210 is equipped
with two modular I/O units (MIOUs) that manage the simple
serial I/O port (SSIO) and the 16-bit parallel host interface
(PHIF16) peripherals. The MIOUs provide transparent DMA
transfers between the peripherals and on-chip dual-port
RAM.
The combination of large on-chip RAM, low power dissipa-
tion, fast instruction cycle times, and efficient I/O manage-
ment makes the DSP16210 an ideal solution in a variety of
emerging applications.
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Optimized for applications requiring large internal mem-
ory, flexible I/O, and high cycle efficiency speech coding,
speech compression, and channel coding
鈥?Large on-chip dual-port RAM (60 Kwords of
DPRAM)鈥攅liminates need for fast external SRAM
鈥?2-input 40-bit arithmetic logic unit (ALU) with
add/compare/select (ACS) for Viterbi acceleration
鈥?3-input adder
鈥?DMA-based I/O鈥攎inimizes DSP core overhead for
I/O processing
鈥?Flexible power management modes for low system
power dissipation
鈥?Provides 200 DSP MIPS
10 ns instruction cycle time at 3 V
Dual 16 x 16-bit multiplication and 40-bit accumulation in
one instruction cycle for efficient algorithm implementa-
tions
31-instruction by 32-bit interruptible do-loop cache for
high-speed, program-efficient, zero-overhead looping
Nested interrupts and three interrupt priority levels for
efficient control and task management operations
On-chip boot ROM with hardware development system
and boot code for flexible downloading
On-chip, programmable, PLL clock synthesizer
Enhanced serial I/O (ESIO) port designed to multi-
plex/demultiplex 64 Kbits/s, 32 Kbits/s, 16 Kbits/s, and 8
Kbits/s channels
26 Mbits/s simple serial I/O (SSIO) port coupled with
DMA to support low-overhead I/O
16-bit parallel host interface (PHIF16) coupled with DMA
to support low-overhead I/O
鈥?Supports either 8-bit or 16-bit external bus configura-
tions (8-bit external configuration supports either 8-bit
or 16-bit logical transfers)
鈥?Supports either
Motorola
1
or
Intel
2
protocols
8-bit control I/O interface for increased flexibility and
lower system costs
IEEE
3
1149.1 test port (JTAG boundary scan)
Full-speed in-circuit emulation hardware development
system on-chip with eight address and two data watch-
point units for efficient application development
Pin compatible with the DSP1620
144-pin TQFP package
1.
Motorola
is a registered trademark of Motorola, Inc.
2.
Intel
is a registered trademark of Intel Corporation.
3.
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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