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DSG5402PGE100 Datasheet

  • DSG5402PGE100

  • FIXED-POINT DIGITAL SIGNAL PROCESSOR

  • 68頁

  • TI

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TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E 鈥?OCTOBER 1998 鈥?REVISED AUGUST 2000
D
Advanced Multibus Architecture With Three
D
D
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17-
脳
17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M
脳
16-Bit
Maximum Addressable External Program
Space
4K x 16-Bit On-Chip ROM
16K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for
Efficient Program and Data Management
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
D
Arithmetic Instructions With Parallel Store
D
D
D
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
鈥?Software-Programmable Wait-State
Generator and Programmable Bank
Switching
鈥?On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
鈥?Two Multichannel Buffered Serial Ports
(McBSPs)
鈥?Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
鈥?Two 16-Bit Timers
鈥?Six-Channel Direct Memory Access
(DMA) Controller
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1
鈥?/div>
(JTAG) Boundary Scan
Logic
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
Available in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
NOTE:This
data sheet is designed to be used in conjunction with the
TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
鈥?IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
2000, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1

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