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DSF10K Datasheet

  • DSF10K

  • EMBEDDED PROGRAMMABLE LOGIC FAMILY

  • 138頁

  • ALTERA   ALTERA

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上傳產(chǎn)品規(guī)格書

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Includes
FLEX 10KA
FLEX 10K
Embedded
Programmable Logic Family
Data Sheet
June 1999, ver. 4.01
Features...
s
s
s
The industry鈥檚 first embedded programmable logic device (PLD)
family, providing System-on-a-Programmable-Chip
TM
integration
鈥?/div>
Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
鈥?/div>
Logic array for general logic functions
High density
鈥?/div>
10,000 to 250,000 typical gates (see
Tables 1
and
2)
鈥?/div>
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
鈥?/div>
MultiVolt
TM
I/O interface support
鈥?5.0-V tolerant input pins in FLEX
10KA devices
鈥?/div>
Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
鈥?/div>
FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Group (PCI SIG)
PCI
Local Bus Specification, Revision 2.2
鈥?/div>
FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
鈥?/div>
Select FLEX 10KA devices support 5.0-V PCI buses with eight or
fewer loads
鈥?/div>
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming any device logic
Table 1. FLEX 10K Device Features
Feature
Typical gates (logic and RAM)
(1)
Maximum system gates
Logic elements (LEs)
Logic array blocks (LABs)
Embedded array blocks (EABs)
Total RAM bits
Maximum user I/O pins
EPF10K10
EPF10K10A
10,000
31,000
576
72
3
6,144
150
EPF10K20
20,000
63,000
1,152
144
6
12,288
189
EPF10K30
EPF10K30A
30,000
69,000
1,728
216
6
12,288
246
EPF10K40
40,000
93,000
2,304
288
8
16,384
189
EPF10K50
EPF10K50V
50,000
116,000
2,880
360
10
20,480
310
Altera Corporation
A-DS-F10K-04.01
1

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