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DS92LV1224TMSA Datasheet

  • DS92LV1224TMSA

  • 40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer

  • 20頁

  • NSC

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DS92LV1023 and DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
June 2002
DS92LV1023 and DS92LV1224
40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
General Description
The DS92LV1023 transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
DS92LV1224 receives the Bus LVDS serial data stream and
transforms it back into a 10-bit wide parallel data bus and
recovers parallel clock. The DS92LV1023 transmits data
over backplanes or cable. The single differential pair data
path makes PCB design easier. In addition, the reduced
cable, PCB trace count, and connector size tremendously
reduce cost. Since one output transmits clock and data bits
serially, it eliminates clock-to-data and data-to-data skew.
The powerdown pin saves power by reducing supply current
when not using either device. Upon power up of the Serial-
izer, you can choose to activate synchronization mode or
allow
the
Deserializer
to
use
the
synchronization-to-random-data feature. By using the syn-
chronization mode, the Deserializer will establish lock to a
signal within specified lock times. In addition, the embedded
clock guarantees a transition on the bus every 12-bit cycle.
This eliminates transmission errors due to charged cable
conditions. Furthermore, you may put the DS92LV1023 out-
put pins into TRI-STATE
廬
to achieve a high impedance
state. The PLL can lock to frequencies between 40 MHz and
66 MHz.
Features
n
Clock recovery from PLL lock to random data patterns.
n
Guaranteed transition every data transfer cycle
n
Chipset (Tx + Rx) power consumption
<
500 mW (typ)
@
66 MHz
n
Single differential pair eliminates multi-channel skew
n
Flow-through pinout for easy PCB layout
n
660 Mbps serial Bus LVDS data rate (at 66 MHz clock)
n
10-bit parallel interface for 1 byte data plus 2 control bits
n
Synchronization mode and LOCK indicator
n
Programmable edge trigger on clock
n
High impedance on receiver inputs when power is off
n
Bus LVDS serial output rated for 27鈩?load
n
Small 28-lead SSOP package
Block Diagrams
10093301
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 2002 National Semiconductor Corporation
DS100933
www.national.com

DS92LV1224TMSA 產(chǎn)品屬性

  • National Semiconductor (TI)

  • 10

  • 1

  • 660 Mbps

  • 3.3 V

  • 1270 mW

  • + 85 C

  • SSOP-28

  • Tube

  • - 40 C

  • SMD/SMT

  • 47

  • 3.6 V

  • 3 V

  • LVCMOS, LVTTL

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