DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
December 2002
DS92LV1021 and DS92LV1210
16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
General Description
The DS92LV1021 transforms a 10-bit wide parallel CMOS/
TTL data bus into a single high speed Bus LVDS serial data
stream with embedded clock. The DS92LV1210 receives the
Bus LVDS serial data stream and transforms it back into a
10-bit wide parallel data bus and separates clock. The
DS92LV1021 may transmit data over heavily loaded back-
planes or 10 meters of cable. The reduced cable, PCB trace
count and connector size saves cost and makes PCB design
layout easier. Clock-to-data and data-to-data skew are elimi-
nated since one output will transmit both clock and all data
bits serially. The powerdown pin is used to save power, by
reducing supply current when either device is not in use. The
Serializer has a synchronization mode that should be acti-
vated upon power-up of the device. The Deserializer will
establish lock to this signal within 1024 cycles, and will flag
Lock status. The embedded clock guarantees a transition on
the bus every 12-bit cycle; eliminating transmission errors
due to charged cable conditions. The DS92LV1021 output
pins may be TRI-STATE
廬
to achieve a high impedance
state. The PLL can lock to frequencies between 16 MHz and
40 MHz.
Features
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Guaranteed transition every data transfer cycle
Single differential pair eliminates multi-channel skew
Flow-through pinout for easy PCB layout
400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
10-bit parallel interface for 1 byte data plus 2 control bits
Synchronization mode and LOCK indicator
Programmable edge trigger on clock
High impedance on receiver inputs when power is off
Bus LVDS serial output rated for 27鈩?load
Small 28-lead SSOP package-MSA
Block Diagrams
10011001
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 2002 National Semiconductor Corporation
DS100110
www.national.com